On 23/02/2022 12:31, Lorenzo Pieralisi wrote:
On Tue, Feb 22, 2022 at 03:47:30PM -0800, Bjorn Andersson wrote:
On Fri 11 Feb 08:12 PST 2022, Lorenzo Pieralisi wrote:
On Fri, Feb 04, 2022 at 05:38:33PM +0300, Dmitry Baryshkov wrote:
On 03/02/2022 18:57, Bjorn Andersson wrote:
On Sat 18 Dec 06:10 PST 2021, Dmitry Baryshkov wrote:
Add optional interconnect support for the 2.7.0/1.9.0 hosts. Set the
bandwidth according to the values from the downstream driver.
What memory transactions will travel this path? I would expect there to
be two different paths involved, given the rather low bw numbers I
presume this is the config path?
I think so. Downstream votes on this path for most of the known SoCs. Two
spotted omissions are ipq8074 and qcs404.
Is there no vote for the data path?
CNSS devices can vote additionally on the MASTER_PCI to memory paths:
For sm845 (45 = MASTER_PCIE):
qcom,msm-bus,vectors-KBps =
<45 512 0 0>,
<45 512 600000 800000>; /* ~4.6Gbps (MCS12) */
On sm8150/sm8250 qca bindings do not contain a vote, but wil6210 does (100 =
MASTER_PCIE_1):
qcom,msm-bus,vectors-KBps =
<100 512 0 0>,
<100 512 600000 800000>; /* ~4.6Gbps (MCS12) */
For sm8450 there are two paths used by cnss:
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
with multiple entries per each path.
So, I'm not sure about these values.
This discussion is gating the series, please let me know if you want me
to cherry-pick the other patches or you will resend the series.
Please pick the other patches and I'll work with Dmitry to conclude how
this is actually connected to the busses inside the SoC.
Hi,
can you resend the series without this patch rebased on top of
v5.17-rc1 please ?
Done. I've posted v6.
--
With best wishes
Dmitry
