Add devicetree YAML binding for SDX65 APCS GCC block. The APCS block
acts as the mailbox controller and also provides a clock output and
takes 3 clock sources (pll, aux, ref) as input.
Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx>
---
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 01e9d91..688ae8b 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -91,6 +91,7 @@ allOf:
compatible:
enum:
- qcom,sdx55-apcs-gcc
+ - qcom,sdx65-apcs-gcc
then:
properties:
clocks:
--
2.7.4
