Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
Add xhci node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index ce18d692175f..08c7c1c772f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
/ {
@@ -718,6 +719,30 @@
status = "disabled";
};
+ xhci: xhci@11200000 {
+ compatible = "mediatek,mt8192-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "host";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg CLK_INFRA_SSUSB>,
+ <&infracfg CLK_INFRA_SSUSB_XHCI>,
+ <&apmixedsys CLK_APMIXED_USBPLL>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
