On Mon, Feb 14, 2022 at 05:48:20PM +0800, 施錕鴻 wrote: > Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx> 於 2022年2月14日 週一 下午5:14寫道： > > > > On Mon, Feb 14, 2022 at 05:03:00PM +0800, 施錕鴻 wrote: > > > Hi, Greg > > > About this issue, my colleague Hammer Hsieh has explained it to > > > you recently in the mail of "[PATCH v7 2/2] serial: sunplus-uart: Add > > > Sunplus > > > SoC UART Driver". The ehci driver and uart one are in the same Sunplus Soc. > > > > I do not know what you are referring to, sorry. Remember we get > > thousands of emails a week. > > > > Please be explicit and make the code work properly for each patch you > > submit. > > > > thanks, > > > > greg k-h > > Hi, Greg > About data incoherence issue between memory bus and peripheral bus. > In case of AXI bus, use non-posted write can avoid data incoherence issue. > What if in case of post write: > Send a specific command after last write command. SDCTRL identify specific > command, means previous write command done. Then send the interrupt > signal to interrupt controller. And then interrupt controller sends done signal > to Master. Master receives done signal, means write command done. Then > issue a interrupt or proceed next write command. I do not understand what you are referring to here as I have no context :(
