Convert Xilinx CAN binding documentation to YAML.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xxxxxxxxxx>
---
BRANCH: yaml
---
.../bindings/net/can/xilinx_can.txt | 61 --------
.../bindings/net/can/xilinx_can.yaml | 146 ++++++++++++++++++
2 files changed, 146 insertions(+), 61 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/can/xilinx_can.txt
create mode 100644 Documentation/devicetree/bindings/net/can/xilinx_can.yaml
diff --git a/Documentation/devicetree/bindings/net/can/xilinx_can.txt b/Documentation/devicetree/bindings/net/can/xilinx_can.txt
deleted file mode 100644
index 100cc40b8510..000000000000
--- a/Documentation/devicetree/bindings/net/can/xilinx_can.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
----------------------------------------------------------
-
-Required properties:
-- compatible : Should be:
- - "xlnx,zynq-can-1.0" for Zynq CAN controllers
- - "xlnx,axi-can-1.00.a" for Axi CAN controllers
- - "xlnx,canfd-1.0" for CAN FD controllers
- - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
-- reg : Physical base address and size of the controller
- registers map.
-- interrupts : Property with a value describing the interrupt
- number.
-- clock-names : List of input clock names
- - "can_clk", "pclk" (For CANPS),
- - "can_clk", "s_axi_aclk" (For AXI CAN and CAN FD).
- (See clock bindings for details).
-- clocks : Clock phandles (see clock bindings for details).
-- tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN).
-- rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
- sequential Rx mode).
-- tx-mailbox-count : Can Tx mailbox buffer count (CAN FD).
-- rx-mailbox-count : Can Rx mailbox buffer count (CAN FD in mailbox Rx
- mode).
-
-
-Example:
-
-For Zynq CANPS Dts file:
- zynq_can_0: can@e0008000 {
- compatible = "xlnx,zynq-can-1.0";
- clocks = <&clkc 19>, <&clkc 36>;
- clock-names = "can_clk", "pclk";
- reg = <0xe0008000 0x1000>;
- interrupts = <0 28 4>;
- interrupt-parent = <&intc>;
- tx-fifo-depth = <0x40>;
- rx-fifo-depth = <0x40>;
- };
-For Axi CAN Dts file:
- axi_can_0: axi-can@40000000 {
- compatible = "xlnx,axi-can-1.00.a";
- clocks = <&clkc 0>, <&clkc 1>;
- clock-names = "can_clk","s_axi_aclk" ;
- reg = <0x40000000 0x10000>;
- interrupt-parent = <&intc>;
- interrupts = <0 59 1>;
- tx-fifo-depth = <0x40>;
- rx-fifo-depth = <0x40>;
- };
-For CAN FD Dts file:
- canfd_0: canfd@40000000 {
- compatible = "xlnx,canfd-1.0";
- clocks = <&clkc 0>, <&clkc 1>;
- clock-names = "can_clk", "s_axi_aclk";
- reg = <0x40000000 0x2000>;
- interrupt-parent = <&intc>;
- interrupts = <0 59 1>;
- tx-mailbox-count = <0x20>;
- rx-fifo-depth = <0x20>;
- };
diff --git a/Documentation/devicetree/bindings/net/can/xilinx_can.yaml b/Documentation/devicetree/bindings/net/can/xilinx_can.yaml
new file mode 100644
index 000000000000..cdf2e4a20662
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/xilinx_can.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/xilinx_can.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+ Xilinx Axi CAN/Zynq CANPS controller Binding
+
+maintainers:
+ - Appana Durga Kedareswara rao <appana.durga.rao@xxxxxxxxxx>
+
+properties:
+ compatible:
+ oneOf:
+ - const: xlnx,zynq-can-1.0
+ description: For Zynq CAN controller
+ - const: xlnx,axi-can-1.00.a
+ description: For Axi CAN controller
+ - const: xlnx,canfd-1.0
+ description: For CAN FD controller
+ - const: xlnx,canfd-2.0
+ description: For CAN FD 2.0 controller
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: |
+ CAN functional clock phandle
+ maxItems: 2
+
+ tx-fifo-depth:
+ description: |
+ CAN Tx fifo depth (Zynq, Axi CAN).
+
+ rx-fifo-depth:
+ description: |
+ CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
+
+ tx-mailbox-count:
+ description: |
+ CAN Tx mailbox buffer count (CAN FD)
+
+ rx-mailbox-count:
+ description: |
+ CAN Rx mailbox buffer count (CAN FD in mailbox Rx mode)
+
+ clock-names:
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: xlnx,zynq-can-1.0
+
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: can_clk
+ - const: pclk
+ required:
+ - tx-fifo-depth
+ - rx-fifo-depth
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: xlnx,axi-can-1.00.a
+
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: can_clk
+ - const: s_axi_aclk
+ required:
+ - tx-fifo-depth
+ - rx-fifo-depth
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: xlnx,canfd-1.0
+
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: can_clk
+ - const: s_axi_aclk
+ required:
+ - tx-mailbox-count
+ - rx-fifo-depth
+
+examples:
+ - |
+ can@e0008000 {
+ compatible = "xlnx,zynq-can-1.0";
+ clocks = <&clkc 19>, <&clkc 36>;
+ clock-names = "can_clk", "pclk";
+ reg = <0xe0008000 0x1000>;
+ interrupts = <0 28 4>;
+ interrupt-parent = <&intc>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+ - |
+ axi-can@40000000 {
+ compatible = "xlnx,axi-can-1.00.a";
+ clocks = <&clkc 0>, <&clkc 1>;
+ clock-names = "can_clk","s_axi_aclk" ;
+ reg = <0x40000000 0x10000>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 59 1>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+ - |
+ canfd@40000000 {
+ compatible = "xlnx,canfd-1.0";
+ clocks = <&clkc 0>, <&clkc 1>;
+ clock-names = "can_clk", "s_axi_aclk";
+ reg = <0x40000000 0x2000>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 59 1>;
+ tx-mailbox-count = <0x20>;
+ rx-fifo-depth = <0x20>;
+ };
--
2.17.1
