GPIO2_IO00 is used by reg_pcie, move the pinmuxing to this node as well.
Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/imx6qdl-mba6.dtsi | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi
index 9aacc1a62189..f4dca20669d6 100644
--- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi
@@ -86,6 +86,8 @@ reg_mba6_3p3v: regulator-mba6-3p3v {
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_regpcie>;
regulator-name = "supply-pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -436,8 +438,6 @@ pinctrl_pcie: pciegrp {
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
- /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
>;
};
@@ -462,6 +462,13 @@ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
>;
};
+ pinctrl_regpcie: regpciegrp {
+ fsl,pins = <
+ /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
--
2.25.1
