On 2022-02-05 18:21, Vidya Sagar wrote:
Subject:
[PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block
From:
Vidya Sagar <vidyas@xxxxxxxxxx>
Date:
2022-02-05, 18:21
To:
<bhelgaas@xxxxxxxxxx>, <lorenzo.pieralisi@xxxxxxx>,
<robh+dt@xxxxxxxxxx>, <thierry.reding@xxxxxxxxx>, <jonathanh@xxxxxxxxxx>
CC:
<kishon@xxxxxx>, <vkoul@xxxxxxxxxx>, <kw@xxxxxxxxx>,
<krzysztof.kozlowski@xxxxxxxxxxxxx>, <p.zabel@xxxxxxxxxxxxxx>,
<mperttunen@xxxxxxxxxx>, <linux-pci@xxxxxxxxxxxxxxx>,
<devicetree@xxxxxxxxxxxxxxx>, <linux-tegra@xxxxxxxxxxxxxxx>,
<linux-kernel@xxxxxxxxxxxxxxx>, <linux-phy@xxxxxxxxxxxxxxxxxxx>,
<kthota@xxxxxxxxxx>, <mmaddireddy@xxxxxxxxxx>, <vidyas@xxxxxxxxxx>,
<sagar.tv@xxxxxxxxx>
Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue
module instantiated once for each PCIe lane between Synopsys DesignWare
core based PCIe IP and Universal PHY block.
Signed-off-by: Vidya Sagar<vidyas@xxxxxxxxxx>
---
.../bindings/phy/phy-tegra194-p2u.yaml | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
index 9a89d05efbda..6ba1f69b1126 100644
--- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
@@ -4,7 +4,7 @@
$id:"http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#";
$schema:"http://devicetree.org/meta-schemas/core.yaml#";
-title: NVIDIA Tegra194 P2U binding
+title: NVIDIA Tegra194 & Tegra234 P2U binding
maintainers:
- Thierry Reding<treding@xxxxxxxxxx>
@@ -12,13 +12,17 @@ maintainers:
description: >
Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
Speed) each interfacing with 12 and 8 P2U instances respectively.
+ Tegra234 has three PHY bricks namesly HSIO, NVHS and GBE (Gigabit Ethernet)
typo: namely
