Hi Richard,
the subject of this patch is too general. Here is my suggestion:
ARM: dts: bcm2711: Fix comment about L2 cache set calculation
But maybe you have a better idea.
Am 05.02.22 um 20:58 schrieb Richard Schleich:
> No functional change.
Please write a simple sentence, explaining why this change is necessary.
Thanks
>
> Signed-off-by: Richard Schleich <rs@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/bcm2711.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
> index d9f31873e711..0f2f26dc5ec6 100644
> --- a/arch/arm/boot/dts/bcm2711.dtsi
> +++ b/arch/arm/boot/dts/bcm2711.dtsi
> @@ -536,7 +536,7 @@ l2: l2-cache0 {
> compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> - cache-sets = <1024>; // 1MiB(size)/64(line-size)=16000ways/16-way set
> + cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
> cache-level = <2>;
> };
> };
