On Thu, Feb 3, 2022 at 6:06 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> RZ/{G2L,V2L} and G2LC SoC use the same carrier board, but the SoM is
> different.
>
> Different pin mapping is possible on SoM. For eg:- RZ/G2L SMARC EVK
> uses SCIF2, whereas RZ/G2LC uses SCIF1 for the serial interface available
> on PMOD1.
>
> This patch adds support for handling the pin mapping differences by moving
> definitions common to RZ/G2L and RZ/G2LC to a common dtsi file.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> v2->v3:-
> * Included common file for RZ/V2L.
> v1->v2:
> * Added Rb tag from Geert.
> * Rebased to latest renesas-devel branch
Will queue in renesas-devel for v5.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
