On Sat, Dec 18, 2021 at 05:10:19PM +0300, Dmitry Baryshkov wrote: > There are two different PCIe controllers and PHYs on SM8450, one having > one lane and another with two lanes. Add support for both PCIe > controllers > > Dependencies: > - https://lore.kernel.org/linux-arm-msm/20211218140223.500390-1-dmitry.baryshkov@xxxxxxxxxx/ > > Changes since v4: > - Add PCIe1 support > - Change binding accordingly, to use qcom,pcie-sm8450-pcie0 and > qcom,pcie-sm8450-pcie1 compatibility strings > - Rebase on top of (pending) pipe_clock cleanup/rework patchset > > Changes since v3: > - Fix pcie gpios to follow defined schema as noted by Rob > - Fix commit message according to Bjorn's suggestions > > Changes since v2: > - Remove unnecessary comment in struct qcom_pcie_cfg > > Changes since v1: > - Fix capitalization/wording of PCI patch subjects > - Add missing gen3x1 specification to PHY table names > > ---------------------------------------------------------------- > Dmitry Baryshkov (5): > dt-bindings: pci: qcom: Document PCIe bindings for SM8450 > PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg > PCI: qcom: Add ddrss_sf_tbu flag > PCI: qcom: Add interconnect support to 2.7.0/1.9.0 ops > PCI: qcom: Add SM8450 PCIe support > > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++- > drivers/pci/controller/dwc/pcie-qcom.c | 101 ++++++++++++++------- > 2 files changed, 91 insertions(+), 32 deletions(-) Need an ACK from pci-qcom maintainers, thanks. Lorenzo
