RZ/G2L and RZ/G2LC SoC use the same carrier board, but the SoM is different. Different pin mapping is possible on SoM. For eg:- RZ/G2L SMARC EVK uses SCIF2, whereas RZ/G2LC uses SCIF1 for the serial interface available on PMOD1. Like wise CAN1 is multiplexed with SCIF1 using SW1[3] or RSPI using SW1[4]. This patch series adds support for handling the pin mapping differences by moving definitions common to RZ/G2L and RZ/G2LC to a common dtsi file. Biju Das (4): arm64: dts: renesas: rzg2l-smarc: Add common dtsi file arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1 .../boot/dts/renesas/r9a07g044c2-smarc.dts | 17 +- .../boot/dts/renesas/r9a07g044l2-smarc.dts | 1 + .../boot/dts/renesas/rz-smarc-common.dtsi | 207 ++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 193 ---------------- .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 30 +++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 75 +++++++ 6 files changed, 314 insertions(+), 209 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi -- 2.17.1
