On Sunday 31 August 2014 11:54:04 Andrew Bresticker wrote: > On Sat, Aug 30, 2014 at 12:57 AM, Arnd Bergmann <arnd@xxxxxxxx> wrote: > > On Friday 29 August 2014 15:14:31 Andrew Bresticker wrote: > >> Define a generic MIPS_GIC_IRQ_BASE which is suitable for Malta and > >> the upcoming Danube board in <mach-generic/irq.h>. Since Sead-3 is > >> different and uses a MIPS_GIC_IRQ_BASE equal to the CPU IRQ base (0), > >> define its MIPS_GIC_IRQ_BASE in <mach-sead3/irq.h>. > >> > >> Signed-off-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx> > >> > > > > Why do you actually have to hardwire an IRQ base? Can't you move > > to the linear irqdomain code for DT based MIPS systems yet? > > Neither Malta nor SEAD-3 use device-tree for interrupts yet, so they > still require a hard-coded IRQ base. For boards using device-tree, I > stuck with a legacy IRQ domain as it allows most of the existing GIC > irqchip code to be reused. I see. Note that we now have irq_domain_add_simple(), which should do the right think in either case: use a legacy domain when a nonzero base is provided for the old boards, but use the simple domain when probed from DT without an irq base. This makes the latter case more memory efficient (it avoids allocating the irq descriptors for every possibly but unused IRQ number) and helps ensure that you don't accidentally rely on hardcoded IRQ numbers for the DT based machines, which would be considered a bug. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
