On Thu, Aug 28, 2014 at 06:11:53PM +0200, Arnd Bergmann wrote:
> On Thursday 28 August 2014 17:31:16 Thierry Reding wrote:
> > + interrupt-controller@60004000 {
> > + compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
> > + reg = <0x60004000 0x40>, /* primary controller */
> > + <0x60004100 0x40>, /* secondary controller */
> > + <0x60004200 0x40>, /* tertiary controller */
> > + <0x60004300 0x40>, /* quaternary controller */
> > + <0x60004400 0x40>; /* quinary controller */
> > + };
> > +
> > timer@60005000 {
> > compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
> >
>
> Don't you need an interrupt-parent and interrupts property here to point to
> the GIC interrupts? I would assume this is a nested irqchip.
No. It's not nested. All SoC interrupts are fed into both the LIC and the
GIC (as SPIs). The LIC also has an interface towards the flowcontroller which
allows waking up the CPU when an interrupt happens, even if the GIC is off.
LIC can also route every interrupt it controls to the AVP.
See also section 3.4.1.4 Interrupt routing of the TRM.
Cheers,
Peter.
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