Hello,
first of all: Sorry for taking so long for the next review round.
> diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
> index f8832cf49384..26c385582c3b 100644
> --- a/arch/microblaze/kernel/timer.c
> +++ b/arch/microblaze/kernel/timer.c
> @@ -251,6 +251,10 @@ static int __init xilinx_timer_init(struct device_node *timer)
> u32 timer_num = 1;
> int ret;
>
> + /* If this property is present, the device is a PWM and not a timer */
> + if (of_property_read_bool(timer, "#pwm-cells"))
> + return 0;
> +
> if (initialized)
> return -EINVAL;
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 21e3b05a5153..cefbf00b4c7e 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -640,4 +640,18 @@ config PWM_VT8500
> To compile this driver as a module, choose M here: the module
> will be called pwm-vt8500.
>
> +config PWM_XILINX
> + tristate "Xilinx AXI Timer PWM support"
> + depends on OF_ADDRESS
> + depends on COMMON_CLK
> + select REGMAP_MMIO
> + help
> + PWM driver for Xilinx LogiCORE IP AXI timers. This timer is
> + typically a soft core which may be present in Xilinx FPGAs.
> + This device may also be present in Microblaze soft processors.
> + If you don't have this IP in your design, choose N.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-xilinx.
> +
> endif
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 708840b7fba8..ea785480359b 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -60,3 +60,4 @@ obj-$(CONFIG_PWM_TWL) += pwm-twl.o
> obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o
> obj-$(CONFIG_PWM_VISCONTI) += pwm-visconti.o
> obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o
> +obj-$(CONFIG_PWM_XILINX) += pwm-xilinx.o
> diff --git a/drivers/pwm/pwm-xilinx.c b/drivers/pwm/pwm-xilinx.c
> new file mode 100644
> index 000000000000..b4d93e8812c6
> --- /dev/null
> +++ b/drivers/pwm/pwm-xilinx.c
> @@ -0,0 +1,319 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2021 Sean Anderson <sean.anderson@xxxxxxxx>
> + *
> + * Limitations:
> + * - When changing both duty cycle and period, we may end up with one cycle
> + * with the old duty cycle and the new period. This is because the counters
> + * may only be reloaded by first stopping them, or by letting them be
> + * automatically reloaded at the end of a cycle. If this automatic reload
> + * happens after we set TLR0 but before we set TLR1 then we will have a
> + * bad cycle. This could probably be fixed by reading TCR0 just before
> + * reprogramming, but I think it would add complexity for little gain.
> + * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
> + * possible by stopping the counters at an appropriate point in the cycle,
> + * but this is not (yet) implemented.
> + * - Only produces "normal" output.
> + * - Always produces low output if disabled.
> + */
> +
> +#include <clocksource/timer-xilinx.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +#include <linux/regmap.h>
> +
> +/*
> + * The following functions are "common" to drivers for this device, and may be
> + * exported at a future date.
> + */
> +u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
> + u64 cycles)
> +{
> + WARN_ON(cycles < 2 || cycles - 2 > priv->max);
> +
> + if (tcsr & TCSR_UDT)
> + return cycles - 2;
> + return priv->max - cycles + 2;
> +}
> +
> +unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv,
> + u32 tlr, u32 tcsr)
> +{
> + u64 cycles;
> +
> + if (tcsr & TCSR_UDT)
> + cycles = tlr + 2;
> + else
> + cycles = (u64)priv->max - tlr + 2;
> +
> + /* cycles has a max of 2^32 + 2 */
If you add "... so the multiplication doesn't overflow." it becomes more
obvious why this comment is there.
> + return DIV64_U64_ROUND_UP(cycles * NSEC_PER_SEC,
> + clk_get_rate(priv->clk));
> +}
> +
> +/*
> + * The idea here is to capture whether the PWM is actually running (e.g.
> + * because we or the bootloader set it up) and we need to be careful to ensure
> + * we don't cause a glitch. According to the data sheet, to enable the PWM we
> + * need to
> + *
> + * - Set both timers to generate mode (MDT=1)
> + * - Set both timers to PWM mode (PWMA=1)
> + * - Enable the generate out signals (GENT=1)
> + *
> + * In addition,
> + *
> + * - The timer must be running (ENT=1)
> + * - The timer must auto-reload TLR into TCR (ARHT=1)
> + * - We must not be in the process of loading TLR into TCR (LOAD=0)
> + * - Cascade mode must be disabled (CASC=0)
> + *
> + * If any of these differ from usual, then the PWM is either disabled, or is
> + * running in a mode that this driver does not support.
> + */
> +#define TCSR_PWM_SET (TCSR_GENT | TCSR_ARHT | TCSR_ENT | TCSR_PWMA)
> +#define TCSR_PWM_CLEAR (TCSR_MDT | TCSR_LOAD)
> +#define TCSR_PWM_MASK (TCSR_PWM_SET | TCSR_PWM_CLEAR)
> +
> +struct xilinx_pwm_device {
> + struct pwm_chip chip;
> + struct xilinx_timer_priv priv;
> +};
> +
> +static inline struct xilinx_timer_priv
> +*xilinx_pwm_chip_to_priv(struct pwm_chip *chip)
> +{
> + return &container_of(chip, struct xilinx_pwm_device, chip)->priv;
> +}
> +
> +static bool xilinx_timer_pwm_enabled(u32 tcsr0, u32 tcsr1)
> +{
> + return ((TCSR_PWM_MASK | TCSR_CASC) & tcsr0) == TCSR_PWM_SET &&
> + (TCSR_PWM_MASK & tcsr1) == TCSR_PWM_SET;
> +}
> +
> +static int xilinx_pwm_apply(struct pwm_chip *chip, struct pwm_device *unused,
> + const struct pwm_state *state)
> +{
> + struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
> + u32 tlr0, tlr1, tcsr0, tcsr1;
> + u64 period_cycles, duty_cycles;
> + unsigned long rate;
> +
> + if (state->polarity != PWM_POLARITY_NORMAL)
> + return -EINVAL;
> +
> + /*
> + * To be representable by TLR, cycles must be between 2 and
> + * priv->max + 2. To enforce this we can reduce the cycles, but we may
> + * not increase them. Caveat emptor: while this does result in more
> + * predictable rounding, it may also result in a completely different
> + * duty cycle (% high time) than what was requested.
> + */
> + rate = clk_get_rate(priv->clk);
> + /* Avoid overflow */
> + period_cycles = min_t(u64, state->period, ULONG_MAX * NSEC_PER_SEC);
on a 64 bit platform ULONG_MAX * NSEC_PER_SEC doesn't fit into an u64
... I think if you replace ULONG_MAX by U32_MAX it works as intended.
> + period_cycles = mul_u64_u32_div(period_cycles, rate, NSEC_PER_SEC);
> + period_cycles = min_t(u64, period_cycles, priv->max + 2);
> + if (period_cycles < 2)
> + return -ERANGE;
> +
> +[...]
> +static void xilinx_pwm_get_state(struct pwm_chip *chip,
> + struct pwm_device *unused,
> + struct pwm_state *state)
> +{
> + struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
> + u32 tlr0, tlr1, tcsr0, tcsr1;
> +
> + regmap_read(priv->map, TLR0, &tlr0);
> + regmap_read(priv->map, TLR1, &tlr1);
> + regmap_read(priv->map, TCSR0, &tcsr0);
> + regmap_read(priv->map, TCSR1, &tcsr1);
> + state->period = xilinx_timer_get_period(priv, tlr0, tcsr0);
> + state->duty_cycle = xilinx_timer_get_period(priv, tlr1, tcsr1);
> + state->enabled = xilinx_timer_pwm_enabled(tcsr0, tcsr1);
> + state->polarity = PWM_POLARITY_NORMAL;
> +
> + /* 100% duty cycle results in constant low output */
> + if (state->period == state->duty_cycle)
There is a corner case: It can happen that
xilinx_timer_get_period(priv, tlr0, tcsr0) ==
xilinx_timer_get_period(priv, tlr1, tcsr1) but not tlr0 == tlr1.
This only happens for clkrate > 1000000000, but given that the fix is
cheap (i.e. check tlr0 == tlr1 instead of state->period ==
state->duty_cycle) I'd suggest to do that.
> + state->duty_cycle = 0;
> +}
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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