Converts net/cortina,gemini-ethernet.txt to yaml
This permits to detect some missing properties like interrupts
Signed-off-by: Corentin Labbe <clabbe@xxxxxxxxxxxx>
---
.../bindings/net/cortina,gemini-ethernet.txt | 92 ------------
.../bindings/net/cortina,gemini-ethernet.yaml | 138 ++++++++++++++++++
2 files changed, 138 insertions(+), 92 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
create mode 100644 Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml
diff --git a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
deleted file mode 100644
index 6c559981d110..000000000000
--- a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
+++ /dev/null
@@ -1,92 +0,0 @@
-Cortina Systems Gemini Ethernet Controller
-==========================================
-
-This ethernet controller is found in the Gemini SoC family:
-StorLink SL3512 and SL3516, also known as Cortina Systems
-CS3512 and CS3516.
-
-Required properties:
-- compatible: must be "cortina,gemini-ethernet"
-- reg: must contain the global registers and the V-bit and A-bit
- memory areas, in total three register sets.
-- syscon: a phandle to the system controller
-- #address-cells: must be specified, must be <1>
-- #size-cells: must be specified, must be <1>
-- ranges: should be state like this giving a 1:1 address translation
- for the subnodes
-
-The subnodes represents the two ethernet ports in this device.
-They are not independent of each other since they share resources
-in the parent node, and are thus children.
-
-Required subnodes:
-- port0: contains the resources for ethernet port 0
-- port1: contains the resources for ethernet port 1
-
-Required subnode properties:
-- compatible: must be "cortina,gemini-ethernet-port"
-- reg: must contain two register areas: the DMA/TOE memory and
- the GMAC memory area of the port
-- interrupts: should contain the interrupt line of the port.
- this is nominally a level interrupt active high.
-- resets: this must provide an SoC-integrated reset line for
- the port.
-- clocks: this should contain a handle to the PCLK clock for
- clocking the silicon in this port
-- clock-names: must be "PCLK"
-
-Optional subnode properties:
-- phy-mode: see ethernet.txt
-- phy-handle: see ethernet.txt
-
-Example:
-
-mdio-bus {
- (...)
- phy0: ethernet-phy@1 {
- reg = <1>;
- device_type = "ethernet-phy";
- };
- phy1: ethernet-phy@3 {
- reg = <3>;
- device_type = "ethernet-phy";
- };
-};
-
-
-ethernet@60000000 {
- compatible = "cortina,gemini-ethernet";
- reg = <0x60000000 0x4000>, /* Global registers, queue */
- <0x60004000 0x2000>, /* V-bit */
- <0x60006000 0x2000>; /* A-bit */
- syscon = <&syscon>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gmac0: ethernet-port@0 {
- compatible = "cortina,gemini-ethernet-port";
- reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
- <0x6000a000 0x2000>; /* Port 0 GMAC */
- interrupt-parent = <&intcon>;
- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon GEMINI_RESET_GMAC0>;
- clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
- clock-names = "PCLK";
- phy-mode = "rgmii";
- phy-handle = <&phy0>;
- };
-
- gmac1: ethernet-port@1 {
- compatible = "cortina,gemini-ethernet-port";
- reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
- <0x6000e000 0x2000>; /* Port 1 GMAC */
- interrupt-parent = <&intcon>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon GEMINI_RESET_GMAC1>;
- clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
- clock-names = "PCLK";
- phy-mode = "rgmii";
- phy-handle = <&phy1>;
- };
-};
diff --git a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml
new file mode 100644
index 000000000000..294977fd32f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cortina Systems Gemini Ethernet Controller
+
+maintainers:
+ - Linus Walleij <linus.walleij@xxxxxxxxxx>
+
+description: |
+ This ethernet controller is found in the Gemini SoC family:
+ StorLink SL3512 and SL3516, also known as Cortina Systems
+ CS3512 and CS3516.
+
+properties:
+ compatible:
+ const: cortina,gemini-ethernet
+
+ reg:
+ minItems: 3
+ description: must contain the global registers and the V-bit and A-bit
+ memory areas, in total three register sets.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+#The subnodes represents the two ethernet ports in this device.
+#They are not independent of each other since they share resources
+#in the parent node, and are thus children.
+patternProperties:
+ "^ethernet-port@[0-9]+$":
+ type: object
+ description: contains the resources for ethernet port
+ allOf:
+ - $ref: ethernet-controller.yaml#
+ properties:
+ compatible:
+ const: cortina,gemini-ethernet-port
+
+ reg:
+ minItems: 2
+ items:
+ - description: DMA/TOE memory
+ - description: GMAC memory area of the port
+
+ interrupts:
+ maxItems: 1
+ description: should contain the interrupt line of the port.
+ this is nominally a level interrupt active high.
+
+ resets:
+ maxItems: 1
+ description: this must provide an SoC-integrated reset line for the port.
+
+ clocks:
+ maxItems: 1
+ description: this should contain a handle to the PCLK clock for
+ clocking the silicon in this port
+
+ clock-names:
+ const: PCLK
+
+ required:
+ - reg
+ - compatible
+ - interrupts
+ - resets
+ - clocks
+ - clock-names
+
+required:
+ - compatible
+ - reg
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/cortina,gemini-clock.h>
+ #include <dt-bindings/reset/cortina,gemini-reset.h>
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy@3 {
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+
+ ethernet@60000000 {
+ compatible = "cortina,gemini-ethernet";
+ reg = <0x60000000 0x4000>, /* Global registers, queue */
+ <0x60004000 0x2000>, /* V-bit */
+ <0x60006000 0x2000>; /* A-bit */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gmac0: ethernet-port@0 {
+ compatible = "cortina,gemini-ethernet-port";
+ reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
+ <0x6000a000 0x2000>; /* Port 0 GMAC */
+ interrupt-parent = <&intcon>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon GEMINI_RESET_GMAC0>;
+ clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
+ clock-names = "PCLK";
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ };
+
+ gmac1: ethernet-port@1 {
+ compatible = "cortina,gemini-ethernet-port";
+ reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
+ <0x6000e000 0x2000>; /* Port 1 GMAC */
+ interrupt-parent = <&intcon>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon GEMINI_RESET_GMAC1>;
+ clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
+ clock-names = "PCLK";
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+ };
--
2.34.1
