On Mon, Aug 25, 2014 at 9:22 PM, Stephen Warren <swarren@xxxxxxxxxxxxx> wrote: > On 08/18/2014 11:08 AM, Andrew Bresticker wrote: >> >> In addition to the PCIe and SATA PHYs, the XUSB pad controller also >> supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single >> PCIe or SATA lane and is mapped to one of the three UTMI ports. >> >> The xHCI controller will also send messages intended for the PHY driver, >> so request and listen for messages on the mailbox's PHY channel. > > > I'd like a review from Thierry here as the HW expert. > > I need an ack from LinusW in order to take this pinctrl patch through the > Tegra tree. Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx> Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
