On Wed, 27 Aug 2014, Weike Chen wrote:
> This patch enables suspend and resume mode for the power management, and
> it is based on Josef Ahmad's previous work.
>
> Reviewed-by: Hock Leong Kweh <hock.leong.kweh@xxxxxxxxx>
> Reviewed-by: Shevchenko, Andriy <andriy.shevchenko@xxxxxxxxx>
> Signed-off-by: Weike Chen <alvin.chen@xxxxxxxxx>
> ---
> drivers/gpio/gpio-dwapb.c | 67 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
>
> diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
> index e0ab988..1055cb3 100644
> --- a/drivers/gpio/gpio-dwapb.c
> +++ b/drivers/gpio/gpio-dwapb.c
> @@ -560,10 +560,77 @@ static const struct of_device_id dwapb_of_match[] = {
> };
> MODULE_DEVICE_TABLE(of, dwapb_of_match);
>
> +#if defined CONFIG_PM_SLEEP
> +/* Store GPIO context across system-wide suspend/resume transitions */
> +static struct gpio_saved_regs {
> + unsigned long data;
> + unsigned long dir;
> + unsigned long int_en;
> + unsigned long int_mask;
> + unsigned long int_type;
> + unsigned long int_pol;
> + unsigned long int_deb;
> +} saved_regs;
> +
> +static int dwapb_gpio_suspend(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
> + struct bgpio_chip *bgc = &gpio->ports[0].bgc;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&bgc->lock, flags);
> +
> + saved_regs.int_mask = dwapb_read(gpio, GPIO_INTMASK);
> + saved_regs.int_en = dwapb_read(gpio, GPIO_INTEN);
> + saved_regs.int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
> + saved_regs.int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
> + saved_regs.int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
> + saved_regs.dir = dwapb_read(gpio, GPIO_SWPORTA_DDR);
> + saved_regs.data = dwapb_read(gpio, GPIO_SWPORTA_DR);
Hello,
The DesignWare GPIO IP can be configured to have ports a, b, c, and d. So
you will need to save and restore any ports that are present. I think
that *some* configurations of the IP include a register that can tell us
how it was configured, but that register is also optional :) I don't have
confidence that we can read/write the registers blindly whether they are
known to be there or not. So you may be stuck with looking at the
device tree or platform data to know whether banks b, c, or d exist.
Alan
> +
> + /* Mask out interrupts */
> + dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
> +
> + spin_unlock_irqrestore(&bgc->lock, flags);
> +
> + return 0;
> +}
> +
> +static int dwapb_gpio_resume(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
> + struct bgpio_chip *bgc = &gpio->ports[0].bgc;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&bgc->lock, flags);
> +
> + dwapb_write(gpio, GPIO_SWPORTA_DR, saved_regs.data);
> + dwapb_write(gpio, GPIO_SWPORTA_DDR, saved_regs.dir);
> + dwapb_write(gpio, GPIO_INTTYPE_LEVEL, saved_regs.int_type);
> + dwapb_write(gpio, GPIO_INT_POLARITY, saved_regs.int_pol);
> + dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, saved_regs.int_deb);
> + dwapb_write(gpio, GPIO_INTEN, saved_regs.int_en);
> + dwapb_write(gpio, GPIO_INTMASK, saved_regs.int_mask);
> +
> + /* Clear out spurious interrupts */
> + dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
> +
> + spin_unlock_irqrestore(&bgc->lock, flags);
> +
> + return 0;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
> + dwapb_gpio_resume);
> +
> static struct platform_driver dwapb_gpio_driver = {
> .driver = {
> .name = "gpio-dwapb",
> .owner = THIS_MODULE,
> + .pm = &dwapb_gpio_pm_ops,
> .of_match_table = of_match_ptr(dwapb_of_match),
> },
> .probe = dwapb_gpio_probe,
> --
> 1.7.9.5
>
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