Re: [PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X)

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On 08/14/2014 12:55 PM, Mark Rutland wrote:
On Wed, Aug 13, 2014 at 04:00:40PM +0100, suravee.suthikulpanit@xxxxxxx wrote:
From: Suravee Suthikulpanit <Suravee.Suthikulpanit@xxxxxxx>

ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.

The patch introduces a new property in ARM gic binding, the v2m subnode.
It is optional.

Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@xxxxxxx>
Cc: Mark Rutland <Mark.Rutland@xxxxxxx>
Cc: Marc Zyngier <Marc.Zyngier@xxxxxxx>
Cc: Jason Cooper <jason@xxxxxxxxxxxxxx>
Cc: Catalin Marinas <Catalin.Marinas@xxxxxxx>
Cc: Will Deacon <Will.Deacon@xxxxxxx>
---
  Documentation/devicetree/bindings/arm/gic.txt |  32 ++++
  drivers/irqchip/Kconfig                       |   7 +
  drivers/irqchip/Makefile                      |   1 +
  drivers/irqchip/irq-gic-v2m.c                 | 215 ++++++++++++++++++++++++++
  drivers/irqchip/irq-gic.c                     |  75 +++++----
  drivers/irqchip/irq-gic.h                     |  48 ++++++
  6 files changed, 348 insertions(+), 30 deletions(-)
  create mode 100644 drivers/irqchip/irq-gic-v2m.c
  create mode 100644 drivers/irqchip/irq-gic.h

diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 5573c08..8a64179 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -95,3 +95,35 @@ Example:
                       <0x2c006000 0x2000>;
                 interrupts = <1 9 0xf04>;
         };
+
+
+* GICv2m extension for MSI/MSI-x support (Optional)
+
+Certain revision of GIC-400 supports MSI/MSI-x via V2M register frame.
+This is enabled by specifying v2m sub-node.
+
+Required properties:
+
+- msi-controller : Identifies the node as an MSI controller.
+
+- reg : GICv2m MSI interface register base and size
+
+Example:
+
+       interrupt-controller@e1101000 {
+               compatible = "arm,gic-400";
+               #interrupt-cells = <3>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               interrupt-controller;
+               interrupts = <1 8 0xf04>;
+               ranges = <0 0 0 0xe1100000 0 0x100000>;
+               reg = <0x0 0xe1110000 0 0x01000>,
+                     <0x0 0xe112f000 0 0x02000>,
+                     <0x0 0xe1140000 0 0x10000>,
+                     <0x0 0xe1160000 0 0x10000>;
+               v2m {
+                       msi-controller;
+                       reg = <0x0 0x80000 0 0x1000>;
+               };
+       };

[...]

@@ -1009,6 +1012,16 @@ gic_of_init(struct device_node *node, struct device_node *parent)
         if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
                 percpu_offset = 0;

+       gic_data[gic_cnt].irq_chip = &gic_chip;
+
+       /* Currently, we only support one v2m subnode. */
+       child = of_get_child_by_name(node, "v2m");
+       if (child) {
+               ret = gicv2m_of_init(child, &gic_data[gic_cnt]);
+               if (ret)
+                       return ret;
+       }

I can't see how you'd sanely expand this to multiple children, which was
the main point of having a separate node for the M block.

Give the M block a compatible string and look for children with that
string.

Thanks,
Mark.

Good point. I can try that.

Thank,

Suravee
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