On Thu 06 Jan 2022 at 09:12, Miquel Raynal <miquel.raynal@xxxxxxxxxxx> wrote:
> liang.yang@xxxxxxxxxxx wrote on Thu, 6 Jan 2022 11:31:30 +0800:
>
>> Change-Id: I1425b491d8b95061e1ce358ef33143433fc94d24
>> ---
>> .../bindings/mtd/amlogic,meson-nand.txt | 18 +++---------------
>
> I forgot to mention, while you're at it, after fixing the bindings,
> could you please convert it to yaml?
>
>> 1 file changed, 3 insertions(+), 15 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> index 5794ab1147c1..37f16fe4fe66 100644
>> --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> @@ -14,11 +14,6 @@ Required properties:
>> - clock-names: Should contain the following:
>> "core" - NFC module gate clock
>> "device" - device clock from eMMC sub clock controller
If I refer to the related driver change, this is not true anymore and
should be updated
>> - "rx" - rx clock phase
>> - "tx" - tx clock phase
>> -
>> -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
>> - controller port C
>>
>> Optional children nodes:
>> Children nodes represent the available nand chips.
>> @@ -28,11 +23,6 @@ see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindi
>>
>> Example demonstrate on AXG SoC:
>>
>> - sd_emmc_c_clkc: mmc@7000 {
>> - compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
>> - reg = <0x0 0x7000 0x0 0x800>;
>> - };
>> -
>> nand-controller@7800 {
>> compatible = "amlogic,meson-axg-nfc";
>> reg = <0x0 0x7800 0x0 0x100>;
>> @@ -41,11 +31,9 @@ Example demonstrate on AXG SoC:
>> interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
>>
>> clocks = <&clkc CLKID_SD_EMMC_C>,
>> - <&sd_emmc_c_clkc CLKID_MMC_DIV>,
>> - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>,
>> - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>;
>> - clock-names = "core", "device", "rx", "tx";
>> - amlogic,mmc-syscon = <&sd_emmc_c_clkc>;
>> + <&clkc CLKID_FCLK_DIV2>;
>> + clock-names = "core", "device";
If you want to re-implement the mmc clock part directly in the nand
driver, you should provide both clock inputs, like the mmc driver (in
addition to the pclk) ... Even if you plan on using only FDIV2 in the
driver, this what the HW is.
Something like:
clock-names = "core", "clkin0", "clkin1";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
>> + sd_emmc_c_clkc = <0xffe07000>;
This is not how you provide memory regions
>>
>> pinctrl-names = "default";
>> pinctrl-0 = <&nand_pins>;
>
>
> Thanks,
> Miquèl
