On 12/14/21 2:05 PM, Pratyush Yadav wrote:
On 08/12/21 05:45PM, Dinh Nguyen wrote:
On Mon, Dec 6, 2021 at 9:51 PM Pratyush Yadav <p.yadav@xxxxxx> wrote:
On 03/12/21 12:17PM, Dinh Nguyen wrote:
The QSPI controller on Intel's SoCFPGA platform does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash.
The module/revision ID is written in the MODULE_ID register. For this
variance, bits 23-8 is 0x0010.
When I looked at your original patches I was under the impression that
this was a SoCFPGA specific thing and did not apply to other
implementation of the IP in general.
If this is indeed a generic thing and we can detect it via the MODULE_ID
register [0], then why not just read that register at probe time and
apply this quirk based on the ID? Why then do we need a separate
compatible at all?
[0] I would like to see it stated explicitly somewhere that version
0x0010 does not support the WR_COMPLETION_CTRL register.
I cannot for sure confirm that this condition applies to only 0x0010
version of the
IP. I can verify that the IP that is in all 3 generations of SoCFPGA
devices, all have
MODULE_ID value of 0x0010 and all do not have the WR_COMPLETION_CTRL
register implemented.
I agree with Rob here. If you are not sure that this is a generic IP
thing then you should not use a generic compatible.
I think using the binding of "intel,socfpga-qspi" should be fine? If we
go by the MODULE_ID value as a indicator of versions, then the version
hasn't changed for all revisions of the SoCFPGA, dating back to the
original Cyclone5, which was introduced in 2012.
Thanks,
Dinh
