On Fri, Dec 10, 2021 at 09:10:38PM +0100, Miquel Raynal wrote: > Describe two new memories modes: > - A stacked mode when the bus is common but the address space extended > with an additinals wires. > - A parallel mode with parallel busses accessing parallel flashes where > the data is spread. > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > --- > .../bindings/spi/spi-peripheral-props.yaml | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml > index 5dd209206e88..4194fee8f556 100644 > --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml > +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml > @@ -82,6 +82,35 @@ properties: > description: > Delay, in microseconds, after a write transfer. > > + stacked-memories: > + $ref: /schemas/types.yaml#/definitions/uint64-matrix matrix or... > + description: Several SPI memories can be wired in stacked mode. > + This basically means that either a device features several chip > + selects, or that different devices must be seen as a single > + bigger chip. This basically doubles (or more) the total address > + space with only a single additional wire, while still needing > + to repeat the commands when crossing a chip boundary. The size of > + each chip should be provided as members of the array. array? Sounds like an array from the description as there is only 1 element, the size. > + minItems: 2 > + maxItems: 2 > + items: > + maxItems: 1 This says you can only have 2 64-bit entries. Probably not what you want. This looks like a case for a maxItems 'should be enough for now' type of value. > + > + parallel-memories: > + $ref: /schemas/types.yaml#/definitions/uint64-matrix > + description: Several SPI memories can be wired in parallel mode. > + The devices are physically on a different buses but will always > + act synchronously as each data word is spread across the > + different memories (eg. even bits are stored in one memory, odd > + bits in the other). This basically doubles the address space and > + the throughput while greatly complexifying the wiring because as > + many busses as devices must be wired. The size of each chip should > + be provided as members of the array. > + minItems: 2 > + maxItems: 2 > + items: > + maxItems: 1 > + > # The controller specific properties go here. > allOf: > - $ref: cdns,qspi-nor-peripheral-props.yaml# > -- > 2.27.0 > >
