On Thu, Dec 2, 2021 at 10:52 AM Herve Codina <herve.codina@xxxxxxxxxxx> wrote:
>
> IRQ 0..7 are not supported by the driver for SPEAr320 SOC family.
>
> IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT).
> Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned
> as follow:
> IRQ 6 - NGPIO_INTR: Combined status of edge programmable
> interrupts from GPIO ports
> IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun
> IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty
> IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun
> IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO
> IRQ 1 - Reserved
> IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports
>
> Add support for these IRQs in SPEAr320 SOC family.
>
> Signed-off-by: Herve Codina <herve.codina@xxxxxxxxxxx>
Acked-by: Arnd Bergmann <arnd@xxxxxxxx>
I took patches 4 and 6 into the soc tree now.
Arnd
