On Tue, Dec 07, 2021 at 01:46:49PM +0000, Robin Murphy wrote: [...] > > [ 28.854767] arm-smmu-v3-pmcg arm-smmu-v3-pmcg.15.auto: iidr=0x0 > > > > Please confirm if this is expected or not? I think this might > > introduce difficulty for John for the PMU event alias patches, which > > is dependent on a non-zero IIDR. > > Yes, from previous discussions I believe the HiSilicon implementations don't > have much meaningful ID information at all (hence why we have to match ACPI > table headers to identify the counter erratum). My trick only works for Arm > Ltd. implementations since they happen to have the IMP-DEF CoreSight > registers with the same information as would be in the future IIDR. > > To clarify, the proposal at this point is to write up JSON files for > MMU-600/MMU-700, based on this patch, in order to pipe-clean the process for > future SMMUv3.3 PMCG implementations with real IIDRs. > > Whether other implementers might retroactively define "equivalent" IIDR > values for their existing implementations in a way we could potentially > quirk in the driver is an orthogonal question. Agreed, it makes sense that supports the standard IP modules in the mainline kernel at this stage. Thanks for explanation. Leo
