On 12/7/21 9:43 AM, Tudor Ambarus wrote: > On 12/7/21 9:35 AM, Tudor Ambarus wrote: >> On 12/7/21 9:14 AM, Pratyush Yadav wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> On 06/12/21 10:59AM, Miquel Raynal wrote: >>>> Describe two new memories modes: >>>> - A stacked mode when the bus is common but the address space extended >>>> with an additinals wires. >>>> - A parallel mode with parallel busses accessing parallel flashes where >>>> the data is spread. >>>> >>>> Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> >>>> --- >>>> .../bindings/spi/spi-peripheral-props.yaml | 21 +++++++++++++++++++ >>>> 1 file changed, 21 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml >>>> index 5dd209206e88..13aa6a2374c9 100644 >>>> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml >>>> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml >>>> @@ -82,6 +82,27 @@ properties: >>>> description: >>>> Delay, in microseconds, after a write transfer. >>>> >>>> + stacked-memories: >>>> + type: boolean >>> >>> I don't think a boolean is enough to completely describe the memory. >>> Sure, you say the memories are stacked, but where do you specify when to >>> switch the CS? They could be two 512 MiB memories, two 1 GiB memories, >>> or one 512 MiB and one 256 MiB. >> >> If the multi-die flash contains identical dies then the die boundary can be >> determined with flash_size / number_of_cs. Are there any multi die flashes > > but the problem is there, yes, there is still the case where there are stacked > devices with a single cs. We'll need to describe the size of the die in some > way. > Even better, winbond stacks a NOR and a NAND: https://www.winbond.com/hq/product/code-storage-flash-memory/spistack-flash/?__locale=en
