On 12/7/21 9:14 AM, Pratyush Yadav wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 06/12/21 10:59AM, Miquel Raynal wrote: >> Describe two new memories modes: >> - A stacked mode when the bus is common but the address space extended >> with an additinals wires. >> - A parallel mode with parallel busses accessing parallel flashes where >> the data is spread. >> >> Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> >> --- >> .../bindings/spi/spi-peripheral-props.yaml | 21 +++++++++++++++++++ >> 1 file changed, 21 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml >> index 5dd209206e88..13aa6a2374c9 100644 >> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml >> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml >> @@ -82,6 +82,27 @@ properties: >> description: >> Delay, in microseconds, after a write transfer. >> >> + stacked-memories: >> + type: boolean > > I don't think a boolean is enough to completely describe the memory. > Sure, you say the memories are stacked, but where do you specify when to > switch the CS? They could be two 512 MiB memories, two 1 GiB memories, > or one 512 MiB and one 256 MiB. If the multi-die flash contains identical dies then the die boundary can be determined with flash_size / number_of_cs. Are there any multi die flashes with different types of dies? > >> + description: Several SPI memories can be wired in stacked mode. >> + This basically means that either a device features several chip >> + selects, or that different devices must be seen as a single >> + bigger chip. This basically doubles (or more) the total address >> + space with only a single additional wire, while still needing >> + to repeat the commands when crossing a chip boundary. XIP is >> + usually not supported in this mode. >> + >> + parallel-memories: >> + type: boolean > > With this I assume both memories have to be the same size? It looks like the assumption for both cases is that the dies are identical. > >> + description: Several SPI memories can be wired in parallel mode. >> + The devices are physically on a different buses but will always >> + act synchronously as each data word is spread across the >> + different memories (eg. even bits are stored in one memory, odd >> + bits in the other). This basically doubles the address space and >> + the throughput while greatly complexifying the wiring because as >> + many busses as devices must be wired. XIP is usually not >> + supported in this mode. >> + >> # The controller specific properties go here. >> allOf: >> - $ref: cdns,qspi-nor-peripheral-props.yaml# >> -- >> 2.27.0 >> > > -- > Regards, > Pratyush Yadav > Texas Instruments Inc. >
