On 31/10/2021 13:22, Sam Protsenko wrote:
> Right now all devices supported in the driver have the single clock: it
> acts simultaneously as a bus clock (providing register interface
> clocking) and source clock (driving watchdog counter). Some newer Exynos
> chips, like Exynos850, have two separate clocks for that. In that case
> two clocks will be passed to the driver from the resource provider, e.g.
> Device Tree. Provide necessary infrastructure to support that case:
> - use source clock's rate for all timer related calculations
> - use bus clock to gate/ungate the register interface
>
> All devices that use the single clock are kept intact: if only one clock
> is passed from Device Tree, it will be used for both purposes as before.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> ---
> Changes in v2:
> - Reworded commit message to be more formal
> - Used separate "has_src_clk" trait to tell if source clock is present
> - Renamed clock variables to match their purpose
> - Removed caching source clock rate, obtaining it in place each time instead
> - Renamed err labels for more consistency
>
> drivers/watchdog/s3c2410_wdt.c | 52 +++++++++++++++++++++++++---------
> 1 file changed, 39 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index fdb1a1e9bd04..c733917c5470 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -118,7 +118,9 @@ struct s3c2410_wdt_variant {
>
> struct s3c2410_wdt {
> struct device *dev;
> - struct clk *clock;
> + struct clk *bus_clk; /* for register interface (PCLK) */
> + struct clk *src_clk; /* for WDT counter */
> + bool has_src_clk;
Why do you need the has_src_clk value? If clk_get() fails, just store
there NULL and clk API will handle it.
Best regards,
Krzysztof
