Quoting Srinivasa Rao Mandadapu (2021-10-26 05:19:23) > Update description for RX and TX cgcr register control property required for > soundwire version 1.6.0 and above. > > Signed-off-by: Srinivasa Rao Mandadapu <srivasam@xxxxxxxxxxxxxx> > Co-developed-by: Venkata Prasad Potturu <potturu@xxxxxxxxxxxxxx> > Signed-off-by: Venkata Prasad Potturu <potturu@xxxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt > index b93a2b3..91b9086 100644 > --- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt > +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt > @@ -150,6 +150,15 @@ board specific bus parameters. > or applicable for the respective data port. > More info in MIPI Alliance SoundWire 1.0 Specifications. > > +- qcom,swrm-hctl-reg: > + Usage: optional > + Value type: <prop-encoded-array> > + Definition: The base address of SoundWire RX and TX cgcr register > + address space. cgcr is "clock gate control register"? > + This is to update soundwire master rxtx cgcr register field to > + make clock gating control as software controllable for RX path and > + TX path which is required for SoundWire version 1.6.0 and above. Nak. Use clk APIs to control clks, not direct MMIO writes into a different device.
