> -----Original Message-----
> From: Rob Herring <robh@xxxxxxxxxx>
> Sent: Tuesday, October 19, 2021 3:18 AM
> To: Richard Zhu <hongxing.zhu@xxxxxxx>
> Cc: l.stach@xxxxxxxxxxxxxx; tharvey@xxxxxxxxxxxxx; kishon@xxxxxx;
> vkoul@xxxxxxxxxx; galak@xxxxxxxxxxxxxxxxxxx; shawnguo@xxxxxxxxxx;
> linux-phy@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> kernel@xxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>
> Subject: Re: [PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and
> name properties
>
> On Tue, Oct 12, 2021 at 04:41:15PM +0800, Richard Zhu wrote:
> > i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties in the
> > binding document.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > ---
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index 2911e565b260..99d9863a69cd 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -128,6 +128,12 @@ properties:
> > enum: [1, 2, 3, 4]
> > default: 1
> >
> > + phys:
> > + description: Phandle of the Generic PHY to the PCIe PHY.
>
> maxItems: 1
>
> And drop 'description'
[Richard Zhu] Hi Rob:
Do you mean to remove all the description, and just like this?
phys:
maxItems: 1
Ok, got that, would be changed as this one in v4 series later.
Thanks.
Best Regards
Richard Zhu
>
> > +
> > + phy-names:
> > + const: pcie-phy
> > +
> > reset-gpio:
> > description: Should specify the GPIO for controlling the PCI bus
> device
> > reset signal. It's not polarity aware and defaults to
> > active-low reset
> > --
> > 2.25.1
> >
> >
