On Mon, Oct 18, 2021 at 7:10 PM Richard Zhu <hongxing.zhu@xxxxxxx> wrote: > > > > -----Original Message----- > > From: Tim Harvey <tharvey@xxxxxxxxxxxxx> > > Sent: Saturday, October 16, 2021 3:59 AM > > To: Richard Zhu <hongxing.zhu@xxxxxxx>; Lucas Stach > > <l.stach@xxxxxxxxxxxxxx> > > Cc: Kishon Vijay Abraham I <kishon@xxxxxx>; vkoul@xxxxxxxxxx; Rob Herring > > <robh@xxxxxxxxxx>; galak@xxxxxxxxxxxxxxxxxxx; Shawn Guo > > <shawnguo@xxxxxxxxxx>; linux-phy@xxxxxxxxxxxxxxxxxxx; Device Tree Mailing > > List <devicetree@xxxxxxxxxxxxxxx>; Linux ARM Mailing List > > <linux-arm-kernel@xxxxxxxxxxxxxxxxxxx>; open list > > <linux-kernel@xxxxxxxxxxxxxxx>; Sascha Hauer <kernel@xxxxxxxxxxxxxx>; > > dl-linux-imx <linux-imx@xxxxxxx> > > Subject: Re: [PATCH v3 0/9] add the imx8m pcie phy driver and imx8mm pcie > > support > > > > On Tue, Oct 12, 2021 at 2:06 AM Richard Zhu <hongxing.zhu@xxxxxxx> > > wrote: > > > > > > refer to the discussion [1] when try to enable i.MX8MM PCIe support, > > > one standalone PCIe PHY driver should be seperated from i.MX PCIe > > > driver when enable i.MX8MM PCIe support. > > > > > > This patch-set adds the standalone PCIe PHY driver suport[1-5], and > > > i.MX8MM PCIe support[6-9] to have whole view to review this patch-set. > > > > > > The PCIe works on i.MX8MM EVK board based the the blkctrl power driver > > > [2] and this PHY driver patch-set. > > > > > > [1] > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc > > > > > hwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F20210510141509.929 > > 120 > > > > > -3-l.stach%40pengutronix.de%2F&data=04%7C01%7Chongxing.zhu%40 > > nxp.c > > > > > om%7C4e3d8ee008d94327f99108d9901634be%7C686ea1d3bc2b4c6fa92cd > > 99c5c3016 > > > > > 35%7C0%7C0%7C637699247319711209%7CUnknown%7CTWFpbGZsb3d8ey > > JWIjoiMC4wLj > > > > > AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000& > > ;sdata= > > > > > Z2TZCpdDUSoqrNB1X%2BXdoYNBe3dBDKUgkA4r%2F0TcdOg%3D&reser > > ved=0 > > > [2] > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc > > > > > hwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fcover%2F202109102026 > > 40 > > > .980366-1-l.stach%40pengutronix.de%2F&data=04%7C01%7Chongxin > > g.zhu% > > > > > 40nxp.com%7C4e3d8ee008d94327f99108d9901634be%7C686ea1d3bc2b4c6 > > fa92cd99 > > > > > c5c301635%7C0%7C0%7C637699247319711209%7CUnknown%7CTWFpbGZ > > sb3d8eyJWIjo > > > > > iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C10 > > 00& > > > ;sdata=5h%2By%2FcBW%2BjFkyplUuN1nB5%2BAFHuwCUJBqvRh1RiPYMo > > %3D&rese > > > rved=0 > > > > > > Main changes v2 --> v3: > > > - Regarding Lucas' comments. > > > - to have a whole view to review the patches, send out the i.MX8MM PCIe > > support too. > > > - move the PHY related bits manipulations of the GPR/SRC to standalone > > PHY driver. > > > - split the dts changes to SOC and board DT, and use the enum instead of > > raw value. > > > - update the license of the dt-binding header file. > > > > > > Changes v1 --> v2: > > > - Update the license of the dt-binding header file to make the license > > > compatible with dts files. > > > - Fix the dt_binding_check errors. > > > > > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 +++ > > > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 79 > > +++++++++++++++++++++++++++++ > > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 53 > > ++++++++++++++++++++ > > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | > > 46 ++++++++++++++++- > > > drivers/pci/controller/dwc/pci-imx6.c | 63 > > ++++++++++++++++++++++- > > > drivers/phy/freescale/Kconfig | 9 > > ++++ > > > drivers/phy/freescale/Makefile | 1 > > + > > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 218 > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > ++++++++++++++++++ > > > include/dt-bindings/phy/phy-imx8-pcie.h | 14 > > ++++++ > > > 9 files changed, 486 insertions(+), 3 deletions(-) > > > > > > [PATCH v3 1/9] dt-bindings: phy: phy-imx8-pcie: Add binding for the > > > [PATCH v3 2/9] dt-bindings: phy: add imx8 pcie phy driver support > > > [PATCH v3 3/9] arm64: dts: imx8mm: add the pcie phy support [PATCH v3 > > > 4/9] arm64: dts: imx8mm-evk: add the pcie phy support [PATCH v3 5/9] > > > phy: freescale: pcie: initialize the imx8 pcie [PATCH v3 6/9] > > > dt-bindings: imx6q-pcie: Add PHY phandles and name [PATCH v3 7/9] > > > arm64: dts: imx8mm: add the pcie support [PATCH v3 8/9] arm64: dts: > > > imx8mm-evk: add the pcie support on imx8mm [PATCH v3 9/9] PCI: imx: > > > add the imx8mm pcie support > > > > Richard and Lucas, > > > > Thanks for your collective work on this series! > > > > I have imx8mm-venice boards to test this on both with and without PCIe > > bridges. I've tested this on top of Shawn's imx/for-next (as blk-ctl has been > > merged there) and end up hanging waiting for PHY ready timeout. > [Richard Zhu] Sorry to reply late. I run the tests based on pci/for-next applied the blk-ctl issue by Lucas [2] in commit. > Can you help to make a re-tests? > As I know that the blk-ctl is not merged yet. > Hi Lucas: > Am I right? > Richard, v5 of blk-ctl is merged into Shawn's for-next tree. > > > > [ 1.454308] imx6q-pcie 33800000.pcie: IO > > 0x001ff80000..0x001ff8ffff -> 0x0 > > [ 1.466538] imx6q-pcie 33800000.pcie: MEM > > 0x0018000000..0x001fefffff -> 0x0 > > [ 1.476344] libphy: fec_enet_mii_bus: probed > > [ 1.602631] phy phy-32f00000.pcie-phy.0: phy init failed --> -110 > > [ 1.608775] imx6q-pcie 33800000.pcie: Waiting for PHY ready timeout! > > > > I can verify that imx8_pcie_phy_probe returns successfully and the the phy > > node (imx6_pcie->phy) was found. > > > > Here is the dt change I made for the imx8mm-venice-gw71xx-0x board that > > has no bridge: > [Richard Zhu] Refer to the changes, the external OSC is used as PCIe REF clock(same to EVK board design), right? Correct, an ext osc is used like EVK. I applied v5 blk-ctl and your v3 series on top of pci/next and came up with the same issue. Do you have a git repo I could try to make sure I'm not missing anything? Also, as Lucas has requested some changes do you have a v4 coming soon that I should wait for to try? I believe this has something to do with the phy reset where some of his changes were requested. Best regards, Tim
