On Sat, Oct 16, 2021 at 04:21:27PM -0700, Bjorn Andersson wrote: > Introduce a binding for the eDP/DP PHY hardware block found in several > different Qualcomm platforms. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> > --- > > Changes since v2: > - None > > .../devicetree/bindings/phy/qcom,edp-phy.yaml | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > new file mode 100644 > index 000000000000..c258e4f7e332 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#"; > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > + > +title: Qualcomm DP/eDP PHY > + > +maintainers: > + - Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> > + > +description: > + The Qualcomm DP/eDP PHY is found in a number of Qualcomm platform and > + provides the physical interface for DisplayPort and Embedded Display Port. > + > +properties: > + compatible: > + enum: > + - qcom,sc8180x-dp-phy > + - qcom,sc8180x-edp-phy Is there a difference between DP and eDP? Perhaps note what that is if so. > + > + reg: > + items: > + - description: PHY base register block > + - description: tx0 register block > + - description: tx1 register block > + - description: PLL register block > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: aux > + - const: cfg_ahb > + > + "#clock-cells": > + const: 1 > + > + "#phy-cells": > + const: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - "#clock-cells" > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + phy@aec2a00 { > + compatible = "qcom,sc8180x-edp-phy"; > + reg = <0x0aec2a00 0x1c0>, > + <0x0aec2200 0xa0>, > + <0x0aec2600 0xa0>, > + <0x0aec2000 0x19c>; > + > + clocks = <&dispcc 0>, <&dispcc 1>; > + clock-names = "aux", "cfg_ahb"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + }; > +... > -- > 2.29.2 > >
