On Sun, Oct 03, 2021 at 08:27:35PM -0500, Samuel Holland wrote:
> The MBUS provides more than address translation and bandwidth control.
> It also provides a PMU to measure bandwidth usage by certain masters,
> and it provides notification via IRQ when they are active or idle.
>
> The MBUS is also tightly integrated with the DRAM controller to provide
> a Memory Dynamic Frequency Scaling (MDFS) feature. In view of this, the
> MBUS binding needs to represent the hardware resources needed for MDFS,
> which include the clocks and MMIO range of the adjacent DRAM controller.
>
> Add the additional resources for the H3 and A64 compatibles, and a new
> example showing how they are used.
>
> Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx>
> ---
> .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 75 ++++++++++++++++++-
> 1 file changed, 72 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
> index e713a6fe4cf7..c1fb404d2fb3 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
> +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
> @@ -33,10 +33,33 @@ properties:
> - allwinner,sun50i-a64-mbus
>
> reg:
> - maxItems: 1
> + minItems: 1
> + items:
> + - description: MBUS interconnect/bandwidth/PMU registers
> + - description: DRAM controller/PHY registers
> +
> + reg-names:
> + items:
> + - const: "mbus"
> + - const: "dram"
Don't need quotes.
Is it your intention that reg-names has to have 2 entries. Usually we
aren't that strict and 1 would be allowed (when reg has 1).
>
> clocks:
> + minItems: 1
> + items:
> + - description: MBUS interconnect module clock
> + - description: DRAM controller/PHY module clock
> + - description: Register bus clock, shared by MBUS and DRAM
> +
> + clock-names:
> + items:
> + - const: "mbus"
> + - const: "dram"
> + - const: "bus"
> +
> + interrupts:
> maxItems: 1
> + description:
> + MBUS PMU activity interrupt.
>
> dma-ranges:
> description:
> @@ -53,13 +76,42 @@ required:
> - clocks
> - dma-ranges
>
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - allwinner,sun8i-h3-mbus
> + - allwinner,sun50i-a64-mbus
> +
> +then:
> + properties:
> + reg:
> + minItems: 2
> +
> + clocks:
> + minItems: 3
> +
> + required:
> + - reg-names
> + - clock-names
> +
> +else:
> + properties:
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> additionalProperties: false
>
> examples:
> - |
> - #include <dt-bindings/clock/sun5i-ccu.h>
> + #include <dt-bindings/clock/sun50i-a64-ccu.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> - mbus: dram-controller@1c01000 {
> + dram-controller@1c01000 {
> compatible = "allwinner,sun5i-a13-mbus";
> reg = <0x01c01000 0x1000>;
> clocks = <&ccu CLK_MBUS>;
> @@ -69,4 +121,21 @@ examples:
> #interconnect-cells = <1>;
> };
>
> + - |
> + dram-controller@1c62000 {
> + compatible = "allwinner,sun50i-a64-mbus";
> + reg = <0x01c62000 0x1000>,
> + <0x01c63000 0x1000>;
> + reg-names = "mbus", "dram";
> + clocks = <&ccu CLK_MBUS>,
> + <&ccu CLK_DRAM>,
> + <&ccu CLK_BUS_DRAM>;
> + clock-names = "mbus", "dram", "bus";
> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + dma-ranges = <0x00000000 0x40000000 0xc0000000>;
> + #interconnect-cells = <1>;
> + };
> +
> ...
> --
> 2.32.0
>
>
