Adds dt binding header for 'ralink,rt2880-reset' resets. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx> --- include/dt-bindings/reset/ralink-rt2880.h | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 include/dt-bindings/reset/ralink-rt2880.h diff --git a/include/dt-bindings/reset/ralink-rt2880.h b/include/dt-bindings/reset/ralink-rt2880.h new file mode 100644 index 000000000000..266ef521a584 --- /dev/null +++ b/include/dt-bindings/reset/ralink-rt2880.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx> + */ + +#ifndef DT_BINDING_RALINK_RT2880_RESET_H +#define DT_BINDING_RALINK_RT2880_RESET_H + +/* + * Ralink RT2880 SoC reset controller register bits. + */ +#define RALINK_RT2880_SYS 0 +#define RALINK_RT2880_MCM 2 +#define RALINK_RT2880_HSDMA 5 +#define RALINK_RT2880_FE 6 +#define RALINK_RT2880_SPDIFTX 7 +#define RALINK_RT2880_TIMER 8 +#define RALINK_RT2880_INT 9 +#define RALINK_RT2880_MC 10 +#define RALINK_RT2880_PCM 11 +#define RALINK_RT2880_PIO 13 +#define RALINK_RT2880_GDMA 14 +#define RALINK_RT2880_NFI 15 +#define RALINK_RT2880_I2C 16 +#define RALINK_RT2880_I2S 17 +#define RALINK_RT2880_SPI 18 +#define RALINK_RT2880_UART1 19 +#define RALINK_RT2880_UART2 20 +#define RALINK_RT2880_UART3 21 +#define RALINK_RT2880_ETH 23 +#define RALINK_RT2880_PCIE0 24 +#define RALINK_RT2880_PCIE1 25 +#define RALINK_RT2880_PCIE2 26 +#define RALINK_RT2880_AUX_STCK 28 +#define RALINK_RT2880_CRYPTO 29 +#define RALINK_RT2880_SDXC 30 +#define RALINK_RT2880_PPE 31 + +#endif /* DT_BINDING_RALINK_RT2880_RESET_H */ -- 2.25.1
