On Wed, Sep 15, 2021 at 06:06:52PM +0900, Daniel Palmer wrote: > Hi Andrew, > > On Wed, 15 Sept 2021 at 00:59, Andrew Lunn <andrew@xxxxxxx> wrote: > > How are the GPIOs mapped to the interrupts? Is it a simple 1:1? > > Unfortunately, no. > I wanted to add the GPIO controller part of this to this same series > but there are some patches in flight for that so it would have been > messy. > You can see that here though: > https://github.com/linux-chenxing/linux/commit/88345dc470bf07d36aa1ddab09551ed33a1cfb22 > > They've really made a mess of this. Their whole GPIO thing is a mess > with no clear logic between the pin names and the register locations > etc. > This IRQ part is no exception. IRQ 0 from this thing isn't for the pin > called GPIO0 or anything sane like that. O.K. Then it sounds like splitting GPIO and the IRQ makes sense. This is the sort of thing which is good to put in the cover letter, explaining why you decided to do it this way. Andrew
