On Tue, Sep 7, 2021 at 4:32 PM Daniel Palmer <daniel@xxxxxxxx> wrote:
> On Tue, 7 Sept 2021 at 23:12, Arnd Bergmann <arnd@xxxxxxxx> wrote:
>
> > > I think the broken memory controller is still there so somehow I'd
> > > need to get the heavy barrier to work in arm64. I haven't yet worked
> > > out if that's even possible.
> >I think I missed that part of the discussion, or I forgot about it already.
> >What is the issue you are referring to here?
>
> Sorry. I should have put a bit more context. This is for the SSD268G
> not the original target of this series. But a similar situation.
> The SSD268G (according to the decompiled device tree) is the same
> hardware as the MSTAR_V7 chips but with a Cortex A53 instead of the
> Cortex A7.
> So it probably has the same memory controller as the MSTAR_V7 stuff
> and that memory controller is not coherent so it needs the kernel to
> make sure memory requests are flushed out to memory before DMA
> happens[0]. For arm I fixed that with the heavy mb callback. With
> arm64 I have no idea how to fix that.
Ok, got it. I do remember the Mstar SoCs having this problem. My feeling
is that this should be possible to implement on arm64 as well using
an erratum fixup with a configuration option, and possibly dynamic patching
to avoid the worst effects when the workaround is built into the kernel
but not needed.
Whether this is acceptable or not is up to the arm64 architecture maintainers
of course.
Arnd
