Hi Arnd, On Tue, 7 Sept 2021 at 23:12, Arnd Bergmann <arnd@xxxxxxxx> wrote: > > I think the broken memory controller is still there so somehow I'd > > need to get the heavy barrier to work in arm64. I haven't yet worked > > out if that's even possible. >I think I missed that part of the discussion, or I forgot about it already. >What is the issue you are referring to here? Sorry. I should have put a bit more context. This is for the SSD268G not the original target of this series. But a similar situation. The SSD268G (according to the decompiled device tree) is the same hardware as the MSTAR_V7 chips but with a Cortex A53 instead of the Cortex A7. So it probably has the same memory controller as the MSTAR_V7 stuff and that memory controller is not coherent so it needs the kernel to make sure memory requests are flushed out to memory before DMA happens[0]. For arm I fixed that with the heavy mb callback. With arm64 I have no idea how to fix that. I'm interested to see how this Airoha EN7523 series goes as if/when I push anything for the SSD268G it'll probably only be for a 32bit kernel. 0 - https://elixir.bootlin.com/linux/latest/source/arch/arm/mach-mstar/mstarv7.c#L61
