Hi Arnd, On 8/11/21 3:46 PM, Arnd Bergmann wrote: > On Wed, Aug 11, 2021 at 3:08 PM Linus Walleij <linus.walleij@xxxxxxxxxx> wrote: >> >> On Thu, Aug 5, 2021 at 7:42 PM Piyush Mehta <piyush.mehta@xxxxxxxxxx> wrote: >> >>> Add Xilinx ZynqMP firmware MMIO APIs support to set and get PS_MODE >>> pins value and status. These APIs create an interface path between >>> mode pin controller driver and low-level API to access GPIO pins. >>> >>> Signed-off-by: Piyush Mehta <piyush.mehta@xxxxxxxxxx> >>> --- >>> Changes in v2: >>> - Added Xilinx ZynqMP firmware MMIO API support to set and get pin >>> value and status. >> >> I doubt this is "GPIO". >> General Purpose? I think not. It seems to be about boot mode. > > Agreed. here is register description. https://www.xilinx.com/html_docs/registers/ug1087/crl_apb___boot_pin_ctrl.html# > >> If you need a userspace ABI, then add sysfs files to this firmware >> driver instead of bridging it to the GPIO subsystem. > > I don't really want custom user interfaces in firmware drivers either. > > What is the high-level description of the 'PS_MODE' here? Is > this perhaps something we already have a user interface for? The reason why this can't be mapped as memory mapped device is that it is in IP which has be secure. That's why routing is done via firmware driver. Based on https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf page 46 PS_MODE Input/Output Dedicated 4-bit boot mode pins sampled on POR deassertion It means ROM just capture boot mode at start that's why they have special meaning and after it is free to use for whatever purpose you want which seems to pretty much as generic purpose I/O. I wrote more comments in reply to Linus already. Thanks, Michal
