On Sat, 7 Aug 2021 at 19:05, Andrew Lunn <andrew@xxxxxxx> wrote: > > On Fri, Aug 06, 2021 at 03:19:03PM +0930, Joel Stanley wrote: > > LiteETH is a small footprint and configurable Ethernet core for FPGA > > based system on chips. > > > > Signed-off-by: Joel Stanley <joel@xxxxxxxxx> > > --- > > .../bindings/net/litex,liteeth.yaml | 62 +++++++++++++++++++ > > 1 file changed, 62 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml > > > > diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml > > new file mode 100644 > > index 000000000000..e2a837dbfdaa > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml > > @@ -0,0 +1,62 @@ > > +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/litex,liteeth.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: LiteX LiteETH ethernet device > > + > > +maintainers: > > + - Joel Stanley <joel@xxxxxxxxx> > > + > > +description: | > > + LiteETH is a small footprint and configurable Ethernet core for FPGA based > > + system on chips. > > + > > + The hardware source is Open Source and can be found on at > > + https://github.com/enjoy-digital/liteeth/. > > + > > +properties: > > + compatible: > > + const: litex,liteeth > > + > > + reg: > > + minItems: 3 > > + items: > > + - description: MAC registers > > + - description: MDIO registers > > + - description: Packet buffer > > Hi Joel > > How configurable is the synthesis? Can the MDIO bus be left out? You > can have only the MDIO bus and no MAC? > > I've not looked at the driver yet, but if the MDIO bus has its own > address space, you could consider making it a standalone > device. Somebody including two or more LiteETH blocks could then have > one shared MDIO bus. That is a supported Linux architecture. It's currently integrated as one device. If you instatined two blocks, you would end up with two mdio controllers, each inside those two liteeth blocks. Obviously being software someone could change that. We've had a few discussions about the infinite possibilities of a soft SoC and what that means for adding driver support to mainline. I think having some basic driver support is useful, particularly as we then get close review as Jakub provided. The liteeth block has seen a lot of use under Linux by risc-v (vexriscv), powerpc (microwatt), and openrisc (mor1k) designs. The microwatt and or1k designs have mainline support, making them easy to test. This driver will support the normal configurations of those platforms. As the soft core project evolves, we can revisit what goes in mainline, how flexible that driver support needs to be, and how best to manage that. > > > + > > + interrupts: > > + maxItems: 1 > > + > > + rx-fifo-depth: > > + description: Receive FIFO size, in units of 2048 bytes > > + > > + tx-fifo-depth: > > + description: Transmit FIFO size, in units of 2048 bytes > > + > > + mac-address: > > + description: MAC address to use > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + mac: ethernet@8020000 { > > + compatible = "litex,liteeth"; > > + reg = <0x8021000 0x100 > > + 0x8020800 0x100 > > + 0x8030000 0x2000>; > > + rx-fifo-depth = <2>; > > + tx-fifo-depth = <2>; > > + interrupts = <0x11 0x1>; > > + }; > > You would normally expect to see some MDIO properties here, a link to > the standard MDIO yaml, etc. Do you have a favourite example that I could follow?
