> Subject: [PATCH v2 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
>
> This adds the description for the i.MX8MM disp blk-ctrl.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Reviewed-by: Peng Fan <peng.fan@xxxxxxx>
> ---
> drivers/soc/imx/imx8m-blk-ctrl.c | 70
> ++++++++++++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c
> b/drivers/soc/imx/imx8m-blk-ctrl.c
> index 3dd17b903636..32eab800a3c6 100644
> --- a/drivers/soc/imx/imx8m-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -433,11 +433,81 @@ static const struct imx8m_blk_ctrl_data
> imx8m_vpu_blk_ctl_dev_data = {
> .num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
> };
>
> +static int imx8mm_disp_power_notifier(struct notifier_block *nb,
> + unsigned long action, void *data) {
> + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
> + power_nb);
> +
> + if (action != GENPD_NOTIFY_ON && action !=
> GENPD_NOTIFY_PRE_OFF)
> + return NOTIFY_OK;
> +
> + /* Enable bus clock and deassert bus reset */
> + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
> + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
> +
> + /*
> + * On power up we have no software backchannel to the GPC to
> + * wait for the ADB handshake to happen, so we just delay for a
> + * bit. On power down the GPC driver waits for the handshake.
> + */
> + if (action == GENPD_NOTIFY_ON)
> + udelay(5);
> +
> +
> + return NOTIFY_OK;
> +}
> +
> +static const struct imx8m_blk_ctrl_domain_data
> imx8m_disp_blk_ctl_domain_data[] = {
> + [IMX8MM_DISPBLK_CSI_BRIDGE] = {
> + .name = "dispblk-csi-bridge",
> + .clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
> + "csi-bridge-core", },
> + .num_clks = 3,
> + .gpc_name = "csi-bridge",
> + .rst_mask = BIT(0) | BIT(1) | BIT(2),
> + .clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
> + },
> + [IMX8MM_DISPBLK_LCDIF] = {
> + .name = "dispblk-lcdif",
> + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
> + .num_clks = 3,
> + .gpc_name = "lcdif",
> + .clk_mask = BIT(6) | BIT(7),
> + },
> + [IMX8MM_DISPBLK_MIPI_DSI] = {
> + .name = "dispblk-mipi-dsi",
> + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
> + .num_clks = 2,
> + .gpc_name = "mipi-dsi",
> + .rst_mask = BIT(5),
> + .clk_mask = BIT(8) | BIT(9),
> + },
> + [IMX8MM_DISPBLK_MIPI_CSI] = {
> + .name = "dispblk-mipi-csi",
> + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
> + .num_clks = 2,
> + .gpc_name = "mipi-csi",
> + .rst_mask = BIT(3) | BIT(4),
> + .clk_mask = BIT(10) | BIT(11),
> + },
> +};
> +
> +static const struct imx8m_blk_ctrl_data imx8m_disp_blk_ctl_dev_data = {
> + .max_reg = 0x2c,
> + .power_notifier_fn = imx8mm_disp_power_notifier,
> + .domains = imx8m_disp_blk_ctl_domain_data,
> + .num_domains = ARRAY_SIZE(imx8m_disp_blk_ctl_domain_data),
> +};
> +
> static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
> {
> .compatible = "fsl,imx8mm-vpu-blk-ctrl",
> .data = &imx8m_vpu_blk_ctl_dev_data
> }, {
> + .compatible = "fsl,imx8mm-disp-blk-ctrl",
> + .data = &imx8m_disp_blk_ctl_dev_data
> + } ,{
> /* Sentinel */
> }
> };
> --
> 2.30.2
