Hi Anand, On Thu, Jul 29, 2021 at 10:11 PM Anand Moon <linux.amoon@xxxxxxxxx> wrote: > > Add reset controller for Ethernet phy reset on every boot for > Amlogic SoC. I think this description does not match what's going on inside the SoC: - for all SoCs earlier than GXL the PHY is external so the reset for the PHY is a GPIO - the reset line you are passing in the .dts belongs to the Ethernet controller on SoCs earlier than GXL - I *believe* that the rset line which you're passing in the .dts belongs to the Ethernet controller AND the built-in MDIO mux on GXL and newer, see also [0] - from how the PRG_ETH registers work I doubt that these are connected to a reset line (as they're managing mostly delays and protocol - so I don't see what would be reset). This is speculation though. Best regards, Martin [0] https://lore.kernel.org/linux-amlogic/553e127c-9839-d15b-d435-c01f18c7be48@xxxxxxxxx/
