On Thu, Jul 29, 2021 at 10:00 AM Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx> wrote: > > On Mon, 26 Jul 2021 06:01:01 PDT (-0700), anup@xxxxxxxxxxxxxx wrote: > > Hi Marc, > > > > On Mon, Jul 26, 2021 at 8:02 PM Marc Zyngier <maz@xxxxxxxxxx> wrote: > >> > >> On Mon, 26 Jul 2021 13:45:20 +0100, > >> Anup Patel <anup@xxxxxxxxxxxxxx> wrote: > >> > > >> > Hi Marc, > >> > > >> > I have taken the approach of IPI domains (like you suggested) in this series. > >> > > >> > What do you think ? > >> > >> I have commented on the irqchip driver. > >> > >> As for the RISC-V specific code, I'll let the architecture maintainers > >> look into it. I guess the elephant in the room is that this spec seems > >> to be evolving, and that there is no HW implementation (how this > >> driver maps on SF's CLINT is anybody's guess). > > There's a long history of interrupt controller efforts from the RISC-V > foundation, and we've yet to have any of them result in hardware. > > > The SiFive CLINT is a more convoluted device and provides M-level > > timer functionality and M-level IPI functionality in one MMIO device. > > > > The RISC-V ACLINT specification is more modular and backward > > compatible with the SiFive CLINT. In fact, a SiFive CLINT device > > can be viewed as a ACLINT MSWI device + ACLINT MTIMER device. > > This means existing RISC-V boards having SiFive CLINT will be > > automatically compliant to the RISC-V ACLINT specification. > > So is there any hardware that this new specification enables? It seems > to be a more convoluted way to describe the same mess we're already in. > I'm not really inclined to take a bunch of code that just does the same > thing via a more complicated specification. > > > Here's the RISC-V ACLINT spec: > > https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc > > > > The RISC-V ACLINT spec is quite stable and we are not seeing any > > further changes hence I sent out RFC PATCHes to get feedback. The > > RISC-V ACLINT spec will be frozen before 2021 end (i.e. before next > > RISC-V summit). > > Have you talked to the other ISA folks about that? > > As far as I can tell this new spec allows for multiple MTIME registers, > which seems to be in direct contradiction to the single -MTIME register The RISC-V ISA spec only mandates a single view of MTIME registers for all the HARTs The RISC-V ISA spec does not mandate a single physical MTIME register. In fact, multi-socket and multi-die systems will end-up having multiple physical MTIME registers so on such systems these physical MTIME registers need to be synchronized with hardware assistance. Please refer to the MTIME synchronization section of ACLINT specification. > as defined in the ISA manual. It also seems to be vaguely incompatible > WRT the definition of SSIP, but I'm not sure that one really matters all > that much as it's not like old software can write the new registers. Please loot at the ACLINT SSWI spec again. The SSIP bit definition is to be modified where mip.SSIP bit is logical OR of software writable bit and external SSIP signal. This way older software which uses SBI call based IPI injection will work fine. In fact, this aspect of SSIP bit is tested on QEMU RISC-V as well. > > I just talked to Krste and Andrew, they say they haven't heard of any of > this. I don't know what's going on over there, but it's very hard to > review anything when I can't even tell where the ISA is defined. Like mentioned in other thread, please first to talk to the actual spec owners first. There are lot of working groups and activities going on in RVI. Regards, Anup > > > The Linux NoMMU kernel (M-level) will use an ACLINT MSWI device > > for IPI support whereas the regular Linux MMU kernel (S-level) will > > use an ACLINT SSWI device for IPI support. > > > > The ACLINT SWI driver is a common IPI driver for both ACLINT > > MSWI (Linux NoMMU) and ACLINT SSWI (Linux MMU). In fact, > > the ACLINT SWI also works for IPI part (i.e. MSWI) of SiFive CLINT. > > > > Regards, > > Anup > > > >> > >> M. > >> > >> -- > >> Without deviation from the norm, progress is not possible.
