Hi Marc, On Mon, Jul 26, 2021 at 8:02 PM Marc Zyngier <maz@xxxxxxxxxx> wrote: > > On Mon, 26 Jul 2021 13:45:20 +0100, > Anup Patel <anup@xxxxxxxxxxxxxx> wrote: > > > > Hi Marc, > > > > I have taken the approach of IPI domains (like you suggested) in this series. > > > > What do you think ? > > I have commented on the irqchip driver. > > As for the RISC-V specific code, I'll let the architecture maintainers > look into it. I guess the elephant in the room is that this spec seems > to be evolving, and that there is no HW implementation (how this > driver maps on SF's CLINT is anybody's guess). The SiFive CLINT is a more convoluted device and provides M-level timer functionality and M-level IPI functionality in one MMIO device. The RISC-V ACLINT specification is more modular and backward compatible with the SiFive CLINT. In fact, a SiFive CLINT device can be viewed as a ACLINT MSWI device + ACLINT MTIMER device. This means existing RISC-V boards having SiFive CLINT will be automatically compliant to the RISC-V ACLINT specification. Here's the RISC-V ACLINT spec: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc The RISC-V ACLINT spec is quite stable and we are not seeing any further changes hence I sent out RFC PATCHes to get feedback. The RISC-V ACLINT spec will be frozen before 2021 end (i.e. before next RISC-V summit). The Linux NoMMU kernel (M-level) will use an ACLINT MSWI device for IPI support whereas the regular Linux MMU kernel (S-level) will use an ACLINT SSWI device for IPI support. The ACLINT SWI driver is a common IPI driver for both ACLINT MSWI (Linux NoMMU) and ACLINT SSWI (Linux MMU). In fact, the ACLINT SWI also works for IPI part (i.e. MSWI) of SiFive CLINT. Regards, Anup > > M. > > -- > Without deviation from the norm, progress is not possible.
