On Wed, Jul 28, 2021 at 12:59 PM Michal Simek <michal.simek@xxxxxxxxxx> wrote: > >> In past we said that we won't be accepting any FPGA description in > >> u-boot/linux projects. I don't think anything has changed from that time > >> and I don't want to end up in situation that we will have a lot of > >> configurations which none else can try and use. > You have to share to customers bitstream. Likely also boot.bin with > PS/PL configuration and other files in it. That's why it will be quite > simple to also share them full DT or DT overlay just for your IP in the > same image. That's possible of course. > Till now I didn't hear any strong argument why this should be accepted. I want to try a new argument: For new bindings a schema is used. The goal is to ensure that the binding schema and the driver fit together. The validation chain is the following: 1) The binding schema is used to validate the device tree. 2) The device tree is used to "validate" the driver by booting. So the kernel tree needs to contain a device tree which uses the binding to build up the complete validation chain. The validation of the driver against the binding is not possible without a device tree. The only option would be to compare driver and binding manually, which is error prone. If device trees with FPGA descriptions are not allowed in the kernel tree, then the kernel tree will never contain complete validation chains für FPGA based IPs. The validation of bindings for FPGA based IPs has to rely on device trees which are maintained out of tree. It is possible/likely that schema validation is not done out of tree. As a result it is more likely that binding and driver do not fit together for FPGA based IPs. In the end the quality of the support for FPGA based IPs would suffer. I suggest allowing a single device tree with FPGA descriptions for a binding of FPGA based IPs. This will build up the complete validation chain in the kernel tree and ensures that binding and driver fit together. This single device tree would form the reference platform for the FPGA based IP. Gerhard
