On Mon, Jul 26, 2021 at 1:46 PM Gerhard Engleder
<gerhard@xxxxxxxxxxxxxxxxxxxxx> wrote:
>
> Combination of Xilinx ZCU104 with Avnet AES-FMC-NETW1-G and TSN endpoint
> Ethernet MAC implemented in FPGA.
>
> Signed-off-by: Gerhard Engleder <gerhard@xxxxxxxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/xilinx/Makefile | 1 +
> arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts | 50 +++++++++++++++++++++
> 2 files changed, 51 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts
>
> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
> index 11fb4fd3ebd4..d0f94ba8ebac 100644
> --- a/arch/arm64/boot/dts/xilinx/Makefile
> +++ b/arch/arm64/boot/dts/xilinx/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-tsnep.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts b/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts
> new file mode 100644
> index 000000000000..19e78b483f44
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +/*
> + * TSN endpoint on Xilinx ZCU104 with Avnet AES-FMC-NETW1-G
> + *
> + * Copyright (C) 2021 Gerhard Engleder <engleder.gerhard@xxxxxxxxx>
> + */
> +
> +/dts-v1/;
> +
> +#include "zynqmp-zcu104-revC.dts"
> +
> +/ {
> + model = "TSN endpoint";
> + compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC",
> + "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
I don't think this will pass schema validation.
In general, do we need a new top-level compatible for every possible
FPGA image? Shouldn't this be an overlay?
Rob
