Enable the gmac controller on the Pine64 Quartz64 Model A.
Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index a3cdb6c2bec6..b239f314b38a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -11,6 +11,7 @@ / {
compatible = "pine64,quartz64-a", "rockchip,rk3566";
aliases {
+ ethernet0 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdhci;
};
@@ -19,6 +20,13 @@ chosen: chosen {
stdout-path = "serial2:1500000n8";
};
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -116,6 +124,29 @@ &cpu3 {
cpu-supply = <&vdd_cpu>;
};
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_3v3>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
@@ -336,6 +367,13 @@ regulator-state-mem {
};
};
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
--
2.25.1
