Hi Michael,
On 7/28/21 6:10 PM, Michael Riesch wrote:
> Signed-off-by: Michael Riesch <michael.riesch@xxxxxxxxxxxxxx>
> ---
> .../boot/dts/rockchip/rk3568-evb1-v10.dts | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
> index 69786557093d..8f4c40d71914 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
> @@ -13,6 +13,11 @@
> model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
> compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
>
> + aliases {
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> + };
> +
> chosen: chosen {
> stdout-path = "serial2:1500000n8";
> };
> @@ -67,6 +72,70 @@
> };
> };
>
> +&gmac0 {
> + phy-mode = "rgmii";
> + clock_in_out = "output";
> +
> + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
> + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
> + assigned-clock-rates = <0>, <125000000>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac0_miim
> + &gmac0_tx_bus2
> + &gmac0_rx_bus2
> + &gmac0_rgmii_clk
> + &gmac0_rgmii_bus>;
> +
> + tx_delay = <0x3c>;
> + rx_delay = <0x2f>;
> +
> + phy-handle = <&rgmii_phy0>;
> + status = "okay";
> +};
> +
> +&gmac1 {
> + phy-mode = "rgmii";
> + clock_in_out = "output";
> +
> + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
> + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
> + assigned-clock-rates = <0>, <125000000>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac1m1_miim
> + &gmac1m1_tx_bus2
> + &gmac1m1_rx_bus2
> + &gmac1m1_rgmii_clk
> + &gmac1m1_rgmii_bus>;
> +
> + tx_delay = <0x4f>;
> + rx_delay = <0x26>;
> +
> + phy-handle = <&rgmii_phy1>;
> + status = "okay";
> +};
> +
> +&mdio0 {
> + rgmii_phy0: phy@0 {
Could you test with ethernet-phy.yaml?
$nodename:
pattern: "^ethernet-phy(@[a-f0-9]+)?$"
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reg = <0x0>;
Sort order is:
compatible
reg
(interrupts)
The rest in alphabetical order.
> + };
> +};
> +
> +&mdio1 {
> + rgmii_phy1: phy@0 {
dito
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reg = <0x0>;
dito
> + };
> +};
> +
> &sdhci {
> bus-width = <8>;
> max-frequency = <200000000>;
>
