On 21-07-21, 11:17, Chunfeng Yun wrote:
> On Tue, 2021-07-20 at 13:55 +0530, Vinod Koul wrote:
> > On 15-07-21, 14:48, Chunfeng Yun wrote:
> > > The controller is designed to use use PLL integer mode, but
> > > in fact used fractional mode for some ones on mt8195, this
> > > causes signal degradation (e.g. eye diagram test fail), fix
> > > it by switching PLL to 26Mhz from default 48Mhz to improve
> > > signal quality.
> > >
> > > Signed-off-by: Chunfeng Yun <chunfeng.yun@xxxxxxxxxxxx>
> > > ---
> > > v2~3: no changes
> > > ---
> > > drivers/phy/mediatek/phy-mtk-tphy.c | 52 +++++++++++++++++++++++++++++
> > > 1 file changed, 52 insertions(+)
> > >
> > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
> > > index 42a1174da6cc..c3dc1763a7eb 100644
> > > --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> > > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> > > @@ -41,6 +41,8 @@
> > >
> > > #define U3P_USBPHYACR0 0x000
> > > #define PA0_RG_U2PLL_FORCE_ON BIT(15)
> > > +#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
> > > +#define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
> > > #define PA0_RG_USB20_INTR_EN BIT(5)
> > >
> > > #define U3P_USBPHYACR1 0x004
> > > @@ -52,6 +54,8 @@
> > > #define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
> > >
> > > #define U3P_USBPHYACR2 0x008
> > > +#define PA2_RG_U2PLL_BW GENMASK(21, 19)
> > > +#define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19)
> > > #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
> > >
> > > #define U3P_USBPHYACR5 0x014
> > > @@ -73,6 +77,14 @@
> > > #define P2C_USB20_GPIO_MODE BIT(8)
> > > #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
> > >
> > > +#define U3P_U2PHYA_RESV 0x030
> > > +#define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b
> > > +#define P2R_RG_U2PLL_FBDIV_48M 0x3c0000
> > > +
> > > +#define U3P_U2PHYA_RESV1 0x044
> > > +#define P2R_RG_U2PLL_REFCLK_SEL BIT(5)
> > > +#define P2R_RG_U2PLL_FRA_EN BIT(3)
> > > +
> > > #define U3D_U2PHYDCR0 0x060
> > > #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
> > >
> > > @@ -277,6 +289,12 @@ enum mtk_phy_version {
> > > struct mtk_phy_pdata {
> > > /* avoid RX sensitivity level degradation only for mt8173 */
> > > bool avoid_rx_sen_degradation;
> > > + /*
> > > + * u2phy should use integer mode instead of fractional mode of
> > > + * 48M PLL, fix it by switching PLL to 26M from default 48M
> > > + * for mt8195
> > > + */
> > > + bool sw_pll_48m_to_26m;
> > > enum mtk_phy_version version;
> > > };
> > >
> > > @@ -456,6 +474,33 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy,
> > > dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
> > > }
> > >
> > > +static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
> > > + struct mtk_phy_instance *instance)
> > > +{
> > > + struct u2phy_banks *u2_banks = &instance->u2_banks;
> > > + void __iomem *com = u2_banks->com;
> > > + u32 tmp;
> > > +
> > > + if (!tphy->pdata->sw_pll_48m_to_26m)
> > > + return;
> > > +
> > > + tmp = readl(com + U3P_USBPHYACR0);
> > > + tmp &= ~PA0_USB20_PLL_PREDIV;
> > > + tmp |= PA0_USB20_PLL_PREDIV_VAL(0);
> > > + writel(tmp, com + U3P_USBPHYACR0);
> > > +
> > > + tmp = readl(com + U3P_USBPHYACR2);
> > > + tmp &= ~PA2_RG_U2PLL_BW;
> > > + tmp |= PA2_RG_U2PLL_BW_VAL(3);
> > > + writel(tmp, com + U3P_USBPHYACR2);
> > > +
> > > + writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
> > > +
> > > + tmp = readl(com + U3P_U2PHYA_RESV1);
> > > + tmp |= P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL;
> > > + writel(tmp, com + U3P_U2PHYA_RESV1);
> > > +}
> > > +
> > > static void u2_phy_instance_init(struct mtk_tphy *tphy,
> > > struct mtk_phy_instance *instance)
> > > {
> > > @@ -941,6 +986,7 @@ static int mtk_phy_init(struct phy *phy)
> > >
> > > switch (instance->type) {
> > > case PHY_TYPE_USB2:
> > > + u2_phy_pll_26m_set(tphy, instance);
> >
> > should this not be set only for MTK_PHY_V3?
> Workaround only for mt8195, HW will fix it for others (V3)
Pls document that in comments here
--
~Vinod
