On Thu, Jun 24, 2021 at 12:43:36PM +0900, Nobuhiro Iwamatsu wrote: > Add device tree bindings for SMU (System Management Unit) controller of > Toshiba Visconti TMPV770x SoC series. > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@xxxxxxxxxxxxx> > --- > .../clock/toshiba,tmpv770x-pismu.yaml | 50 +++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml > > diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml > new file mode 100644 > index 000000000000..18fdf4f2831b > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml > @@ -0,0 +1,50 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings > + > +maintainers: > + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@xxxxxxxxxxxxx> > + > +description: > + Toshia Visconti5 SMU (System Management Unit) which supports the clock > + and resets on TMPV770x. > + > +properties: > + compatible: > + const: toshiba,tmpv7708-pismu > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 Is there a connection to the PLLs? What are the clock inputs? > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pismu: pismu@24200000 { clock-controller@... > + compatible = "toshiba,tmpv7708-pismu"; > + reg = <0 0x24200000 0 0x2140>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + }; > +... > -- > 2.32.0 > >
