Hi Mauro, On Wed, Jul 14, 2021 at 09:14:35AM +0200, Mauro Carvalho Chehab wrote: > Em Tue, 13 Jul 2021 20:26:49 -0600 > Rob Herring <robh@xxxxxxxxxx> escreveu: > > > On Tue, Jul 13, 2021 at 08:28:35AM +0200, Mauro Carvalho Chehab wrote: > > > > + reset-gpios: > > > + description: PCI PERST reset GPIOs > > > + maxItems: 4 > > > > Hiding the 4 ports in the phy? > > Rob, > > I'm not trying to hide anything. > > There are several differences with regards to how PERST# is handled between > HiKey 960 and HiKey 970. > > From hardware perspective, you can see the schematics of both boards: > > https://github.com/96boards/documentation/raw/master/consumer/hikey/hikey960/hardware-docs/HiKey960_SoC_Reference_Manual.pdf > https://www.96boards.org/documentation/consumer/hikey/hikey970/hardware-docs/files/hikey970-schematics.pdf > > The 960 PHY has the SoC directly connected to a PCIE M.2 slot > (model 10130616) without any external bridge chipset. It uses a single > GPIO (GPIO 089) for the PERST# signal, connected via a voltage converter > (from 1.8V to 3.3V). > > $ lspci > 00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01) > > The 970 PHY has an external PCI bridge chipset (PLX Technology PEX 8606). > Besides the bridge, the hardware comes with an Ethernet PCI adapter, a > M.2 slot and a mini-PCIe connector. Each one with its own PERST# signal, > mapped to different GPIO pins, and each one using its own voltage > converter. > > $ lspci > 00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01) > 01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) > 02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) > 02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) > 02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) > 02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) > 02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) > 06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07) > > On other words, there are 4 GPIOs mapped to different PERST# pins in > the hardware: > > - GPIO 56 is connected to the PERST# pin at PEX 8606; > - GPIO 25 is connected to the PERST# pin at the M.2 slot; > - GPIO 220 is connected to the PERST# pin at the PCIe mini slot; > - GPIO 203 is connected to the PERST# pin at the Ethernet chipset. > > Maybe due to different electrical requirements, the hardware design > use different GPIOs instead of feeding them altogether. > > Anyway, the fact is that the PHY on 970 has 4 different GPIOs that are > need in order for the hardware to work. and this is specific to this > particular PHY. > I'm not sure about this. That fact that the PCIe device's PERST# signal wired to different GPIOs doesn't mean that those GPIOs belong to the PHY. Those GPIOs should be independent of the PCIe core controlled manually by the driver. I think this issue is somewhat similar to the one we are dealing on the Qcom platforms [1] where each PCIe device uses a different GPIO and voltage config to operate. And those need to be active for the link training to succeed. So perhaps we should aim for a common solution? The GPIO and voltage layout should be described in DT for each port exposed by the SoC/board. Thanks, Mani [1] https://lkml.org/lkml/2021/6/21/1524
