On Tue, Jul 13, 2021 at 08:28:37AM +0200, Mauro Carvalho Chehab wrote:
> There are several properties there that belong to the PHY
> interface. Drop them, as a new binding file will describe
> the PHY properties for Kirin 960.
Folks are okay with an incompatible change on hikey960?
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx>
> ---
> .../devicetree/bindings/pci/kirin-pcie.txt | 16 +++-------------
> 1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
> index 71cac2b74002..a93a8cfa1afb 100644
> --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
> @@ -10,13 +10,11 @@ Additional properties are described here:
> Required properties
> - compatible:
> "hisilicon,kirin960-pcie"
> -- reg: Should contain rc_dbi, apb, phy, config registers location and length.
> +- reg: Should contain rc_dbi, apb, config registers location and length.
> - reg-names: Must include the following entries:
> "dbi": controller configuration registers;
> "apb": apb Ctrl register defined by Kirin;
> - "phy": apb PHY register defined by Kirin;
> "config": PCIe configuration space registers.
> -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
>
> Optional properties:
>
> @@ -25,8 +23,8 @@ Example based on kirin960:
> pcie@f4000000 {
> compatible = "hisilicon,kirin960-pcie";
> reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
> - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
> - reg-names = "dbi","apb","phy", "config";
> + <0x0 0xF4000000 0 0x2000>;
> + reg-names = "dbi","apb", "config";
> bus-range = <0x0 0x1>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -39,12 +37,4 @@ Example based on kirin960:
> <0x0 0 0 2 &gic 0 0 0 283 4>,
> <0x0 0 0 3 &gic 0 0 0 284 4>,
> <0x0 0 0 4 &gic 0 0 0 285 4>;
> - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
> - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
> - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> - <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
> - clock-names = "pcie_phy_ref", "pcie_aux",
> - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
> - reset-gpios = <&gpio11 1 0 >;
> };
> --
> 2.31.1
>
>
