Quoting Cristian Ciocaltea (2021-06-10 13:05:24)
> There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> clock chain involving AHPPREDIV, H and AHB clocks:
>
> * AHBPREDIV clock is defined as a muxer only, although it also acts as
> a divider.
> * H clock is using a wrong divider register offset
> * AHB is defined as a multi-rate factor clock, but it is actually just
> a fixed pass clock.
>
> Let's provide the following fixes:
>
> * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition.
> * Use the correct register shift value in the OWL_DIVIDER definition
> for H clock
> * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an
> ungated OWL_COMP_FIXED_FACTOR definition.
>
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxx>
> ---
Applied to clk-next
